/************************************************************* * dm270-registers.h *************************************************************/#ifndef __RRLOAD_DM270_REGISTER_H#define __RRLOAD_DM270_REGISTER_H//afraxus#define CADENUX_DM270_PMP 1#include "memconfig.h"/* Memory mapped registers */#define TIMER0_REGISTER_BASE    0x00030000 /* Timer0 */#define TIMER1_REGISTER_BASE	0x00030080 /* Timer1 */#define TIMER2_REGISTER_BASE	0x00030100 /* Timer2 */#define TIMER3_REGISTER_BASE	0x00030180 /* Timer3 */#define SERIAL0_REGISTER_BASE	0x00030200 /* Serial0 */#define SERIAL1_REGISTER_BASE	0x00030280 /* Serial1 */#define UART0_REGISTER_BASE	0x00030300 /* UART0 */#define UART1_REGISTER_BASE	0x00030380 /* UART1 */#define WDT_REGISTER_BASE	0x00030400 /* Watch dog timer */#define MMCSD_REGISTER_BASE     0x00030480 /* MMC/SD */#define INTCTRL_REGISTER_BASE	0x00030500 /* INTC */#define GIO_REGISTER_BASE	0x00030580 /* GIO */#define DSPC_REGISTER_BASE      0x00030600 /* DSP Controller */#define OSD_REGISTER_BASE	0x00030680 /* OSD */#define CCDC_REGISTER_BASE	0x00030700 /* CCD controller */#define PVEN_REGISTER_BASE	0x00030780 /* Preview engine */#define NTSCPAL_REGISTER_BASE	0x00030800 /* NTSC/PAL video encoder */#define CLOCKC_REGISTER_BASE	0x00030880 /* Clock controller */#define BUSC_REGISTER_BASE	0x00030900 /* Bus controller */#define SDRAMC_REGISTER_BASE	0x00030980 /* SDRAM controller */#define EMEMC_REGISTER_BASE	0x00030a00 /* External Memory Interface */#define USB0_REGISTER_BASE      0x00030a80 /* USB 0 */#define USB1_REGISTER_BASE      0x00030b00 /* USB 1 */#define AF_REGISTER_BASE        0x00030b80 /* 3A(AF/AE/AWB) */#define MSTICK1_REGISTER_BASE   0x00030c00 /* Memory Stick 1 */#define MSTICK2_REGISTER_BASE   0x00030c80 /* Memory Stick 2 */#define ATM_REGISTER_BASE       0x00030d00 /* ATM */#define I2C_REGISTER_BASE       0x00030d80 /* I2C */#define ICACHE_REGISTER_BASE    0x00030e00 /* Instruction cache *//* General purpose I/O */#define GIO_DIR0                0x00030580#define GIO_DIR1                0x00030582#define GIO_DIR2                0x00030584#define GIO_BITSET0             0x0003058C#define GIO_BITSET1             0x0003058E#define GIO_BITSET2             0x00030590#define GIO_BITCLR0             0x00030592#define GIO_BITCLR1             0x00030594#define GIO_BITCLR2             0x00030596#if defined(CADENUX_DM270_PMP)	#define GIO_FSEL0		0x000305A4	#define GIO_FSEL1		0x000305A6#endif/** Data **///#if defined(BSPCONF_DM270_INGENIENT_MP4900)//	#if defined(CADENUX_DM270_PMP)	//	#define GIO_DIR0_DATA         0x7EDF	//		#define GIO_DIR0_DATA         0x5EDF	//for pmu(GIO 13)//		#define GIO_DIR1_DATA         0xFFFD  /* clk out #0 bit 16*///		#define GIO_BITSET0_DATA      0x0120//		#define GIO_BITSET0_DATA      0x2120   //FOR PMU(GIO 13)//		#define GIO_BITCLR0_DATA      0x8000//		#define GIO_FSEL0_DATA        0x0300  /* bit 8 set *///	#else//		#define GIO_DIR0_DATA         0x7EDF//		#define GIO_BITSET0_DATA      0x0120//		#define GIO_BITCLR0_DATA      0x8000//	#endif//#endif//#if defined(BSPCONF_DM270_INGENIENT_MDV4100)//	#define GIO_DIR0_DATA         0x7EDF//	#define GIO_DIR1_DATA         0xFFFC//	#define GIO_BITSET0_DATA      0x0120//	#define GIO_BITCLR0_DATA      0x8000//	#define GIO_BITCLR1_DATA      0x0003//#endif//#if defined(BSPCONF_DM270_INGENIENT_TOKRA)//	#  define GIO_BITSET0_DATA      0x8180//	#  define GIO_BITCLR0_DATA      0x0010//	#  define GIO_BITCLR0_DATA2     0x0090//	#  define GIO_DIR0_DATA	        0x7e6f//	#  define GIO_BITSET1_DATA      0x9203//	#  define GIO_BITCLR1_DATA      0x6800//	#  define GIO_DIR1_DATA	        0x05fc//	#  define GIO_BITSET2_DATA      0x0002//	#  define GIO_BITCLR2_DATA      0x0000//	#  define GIO_DIR2_DATA	        0x0001//#endif/* Clock Controller */#define CLOCKC_PLLA             0x00030880 /* PLLA config */#define CLOCKC_PLLB             0x00030882 /* PLLB config */#define CLOCKC_CLKC             0x00030884 /* CLK reverse, source select */#define CLOCKC_SEL              0x00030886 /* PLL selection */#define CLOCKC_DIV              0x00030888 /* DIV ratency config */#define CLOCKC_BYP              0x0003088a /* PLL Bypass config */#define CLOCKC_MMCLK            0x0003088c /* MMC CLK */#define CLOCKC_CTST             0x0003088e /* CTST CLK */#define CLOCKC_MOD0             0x00030890 /* CLK Enable/Disable */#define CLOCKC_MOD1             0x00030892 /* CLK Enable/Disable */#define CLOCKC_MOD2             0x00030894 /* CLK Enable/Disable */#define CLOCKC_LPCTL0           0x00030896 /* SLEEP */#define CLOCKC_LPCTL1           0x00030898 /* Power Down */#define CLOCKC_OSEL             0x0003089a /* General CLK src selection */#define CLOCKC_O0DIV            0x0003089c /* General CLK0 DIV config */#define CLOCKC_O1DIV            0x0003089e /* General CLK1 DIV config */#define CLOCKC_O2DIV            0x000308a0 /* General CLK2 DIV config */#define CLOCKC_PWM0C            0x000308a2 /* PWM0 CLK config */#define CLOCKC_PWM0H            0x000308a4 /* PWM0 H-Level duration config */#define CLOCKC_PWM1C            0x000308a6 /* PWM1 CLK config */#define CLOCKC_PWM1H            0x000308a8 /* PWM1 H-Level duration config *//* Initial Clock Controller Settings *//* TI Recommended values   PLLA: Fin=27 Mhz, M=13, N=2,   PLLA = ( Fin * M / N ) = 27 Mhz * 13 / 2 = 175.5 Mhz   PLLB: Fin=27 Mhz, M=12, N=2,   PLLB = ( Fin * M / N ) = 27 Mhz * 12 / 2 = 162 Mhz    ARM: PLLA / 2 = 87.75 Mhz    DSP: PLLA / 2 = 87.75 Mhz    AXL: PLLA / 1 = 175.5 Mhz  SDRAM: PLLB / 2 = 81 Mhz*///#if defined(BSPCONF_DM270_INGENIENT)//	#if defined(CADENUX_DM270_PMP)//		#define PLLA_DATA  0x00f3 /* PLLA: 108.00 MHz (27MHz * 16 / 4) *///		#define SDRAM_CLK  108000 //	#else//		#define PLLA_DATA  0x00e3 /* PLLA: 101.25 MHz (27MHz * 15 / 4) *///		#define SDRAM_CLK  101250 //	#endif//#  define PLLB_DATA  0x00d1 /* PLLB: 189 MHz (27 MHz * 14 / 2) *///#  define CLKC_DATA  0x07e0 /* set UART[0-1]/TIMER[0-3] clock to PLLIN *///#  define SEL_DATA   0x1011 /* PLLA: SDRAM, PLLB: ACL, DSP, ARM *///#  define DIV_DATA   0x0011//Modified by Lee for test...//#  define SEL_DATA   0x1001 /* PLLA: SDRAM, DSP  PLLB: ACL, ARM *///#  define DIV_DATA   0x0001//#  define SEL_DATA   0x1000 /* PLLA: SDRAM, DSP  PLLB: ACL, ARM *///#  define DIV_DATA   0x0000//#else//#  define PLLA_DATA  0x00E1 /* PLLA config: M=13 N=2 *///#  define PLLB_DATA  0x00C1 /* PLLB config: M=12  N=2 *///#  define CLKC_DATA  0x41E1 /* UARTs source MXI//                               Timer source MXI//                               PLL input clock MXI (test2=0) *///#  define SEL_DATA   0x1011 /* PLL selection: AXL:A, SDRAM:B,//                                              DSP:A, ARM:A *///#  define DIV_DATA   0x0111 /* DIV ratency config: AXL=1, SDRAM=1/2//                                                   DSP=1/2, ARM=1/2 *///#endif/* Calculate the ARM frequency based on the PLL settings */#define PLL_IN     27000000 /* 27.000 Mhz */#define PLLA_M     (((PLLA_DATA & 0x00F0) >> 4) + 1)#define PLLA_N     (((PLLA_DATA & 0x000F) >> 0) + 1)#define PLLB_M     (((PLLB_DATA & 0x00F0) >> 4) + 1)#define PLLB_N     (((PLLB_DATA & 0x000F) >> 0) + 1)#define DIV        (DIV_DATA & 0x00F)#if (SEL_DATA  & 0x0001)#  define ARM_CLK    ((PLL_IN * PLLB_M / PLLB_N) / (DIV + 1))#  define SDRAM_CLK    ((PLL_IN * PLLA_M / PLLA_N) / (DIV + 1))#else#  define ARM_CLK    ((PLL_IN * PLLA_M / PLLA_N) / (DIV + 1))#endif#if defined(BSPCONF_DM270_INGENIENT)# define MMCLK_DATA 0x0002 /* MMC CLK: ARM/3 = 22.5MHz */#else# define MMCLK_DATA 0x0003 /* MMC CLK: ARM/4 = ~ 22 MHz */#endif#define BYPON_DATA  0xFFFF /* PLL Bypass config: BYPASS  *///Modified By Lee...for  power on sequence..//#define BYPOFF_DATA 0x0000 /* PLL Bypass config: NO BYPASS */#define BYPOFF_DATA 0x0100 /* PLL Bypass config: SDRAM: BYPASS, OTHERSS: NOBYPASS */#define MSCLK_DATA  0x0000 /* MS CLK */#define MOD0_DATA   0x07ff /* CLK Enable/Disable: Enable ALL */#define MOD1_DATA   0x01ff /* CLK Enable/Disable: Enable ALL */#define MOD2_DATA   0x2fff /* CLK Enable/Disable: Enable ALL except test */#define LPCTL0_DATA 0x0000 /* SLEEP: Normal */#define LPCTL1_DATA 0x0000 /* Power Down: default */#if defined(CADENUX_DM270_PMP)	#define OSEL_DATA   0x0012 /* General CLK src selection: GIO17 GIO16 */	#define O0DIV_DATA  0x0000 /* General CLK0 DIV config: default */	#define O1DIV_DATA  0x0001 /* General CLK1 DIV config: devided by 4 */	#define O2DIV_DATA  0x0000 /* General CLK2 DIV config: default */#else	#define OSEL_DATA   0x0000 /* General CLK src selection: default */	#define O0DIV_DATA  0x0000 /* General CLK0 DIV config: default */	#define O1DIV_DATA  0x0000 /* General CLK1 DIV config: default */	#define O2DIV_DATA  0x0000 /* General CLK2 DIV config: default */#endif#define PWM0C_DATA  0x0000 /* PWM0 CLK config: default */#define PWM0H_DATA  0x0000 /* PWM0 H-Level duration config: default */#define PWM1C_DATA  0x0000 /* PWM1 CLK config: default */#define PWM1H_DATA  0x0000 /* PWM1 H-Level duration config: default */#define MOD0_DATA_1 0x00e7 /* CLK Enable/Disable: Enable ALL */#define MOD0_DATA_2 0x06ff /* CLK Enable/Disable: ALL Ena exp for CEHIF *//* SDRAM Controller */#define SDRAMC_BUF0             0x00030980 /* D0L */#define SDRAMC_BUF1             0x00030982 /* D0H */#define SDRAMC_BUF2             0x00030984 /* D1L */#define SDRAMC_BUF3             0x00030986 /* D1H */#define SDRAMC_BUF4             0x00030988 /* D2L */#define SDRAMC_BUF5             0x0003098a /* D2H */#define SDRAMC_BUF6             0x0003098c /* D3L */#define SDRAMC_BUF7             0x0003098e /* D3H */#define SDRAMC_BUF8             0x00030990 /* D4L */#define SDRAMC_BUF9             0x00030992 /* D4H */#define SDRAMC_BUFA             0x00030994 /* D5L */#define SDRAMC_BUFB             0x00030996 /* D5H */#define SDRAMC_BUFC             0x00030998 /* D6L */#define SDRAMC_BUFD             0x0003099a /* D6H */#define SDRAMC_BUFE             0x0003099c /* D7L */#define SDRAMC_BUFF             0x0003099e /* D7H */#define SDRAMC_AD0              0x000309a0 /* Address autoincr, SDR address1 */#define SDRAMC_AD1              0x000309a2 /* SDR address2 */#define SDRAMC_BUFCTL           0x000309a4 /* SDR and BUFF control */#define SDRAMC_MODE             0x000309a6 /* SDR mode */#define SDRAMC_REFCTL           0x000309a8 /* DMA select, Refresh control */#define SDRAMC_SDPRTY1          0x000309aa /* Priority1 */#define SDRAMC_SDPRTY2          0x000309ac /* Priority2 */#define SDRAMC_SDPRTY3          0x000309ae /* Priority3 */#define SDRAMC_SDPRTY4          0x000309b0 /* Priority4 */#define SDRAMC_SDPRTY5          0x000309b2 /* Priority5 */#define SDRAMC_SDPRTY6          0x000309b4 /* Priority6 */#define SDRAMC_SDPRTY7          0x000309b6 /* Priority7 */#define SDRAMC_SDPRTY8          0x000309b8 /* Priority8 */#define SDRAMC_SDPRTY9          0x000309ba /* Priority9 */#define SDRAMC_SDPRTY10         0x000309bc /* Priority10 */#define SDRAMC_PRTYON           0x000309be /* PRTY Enable */#define SDRAMC_SDRCTEST         0x000309bE/* SDRAM Controller Initial Settings */#if defined(BSPCONF_DM270_INGENIENT)// afraxus change to SDRAM_TYPE_K4S561632D configuration #define SDMODE_DATA             0x1300#define SDREF_DATA              0x0140#define SDCNT_DATA1             (SDMODE_DATA | 0x0002)#define SDCNT_DATA2             (SDMODE_DATA | 0x0004)#define SDCNT_DATA3             (SDMODE_DATA | 0x0001)/*#define SDMODE_DATA             0x3200#define SDREF_DATA              0x0140#define SDCNT_DATA1             0x3202#define SDCNT_DATA2             0x3204#define SDCNT_DATA3             0x3201*/#elif (BSPCONF_SDRAM_TYPE == SDRAM_TYPE_K4S561632D)/* assumes there are two SDRAM chips for a total of 64 Mbytes */#define SDMODE_DATA             0x1300#define SDREF_DATA              0x0140#define SDCNT_DATA1             (SDMODE_DATA | 0x0002)#define SDCNT_DATA2             (SDMODE_DATA | 0x0004)#define SDCNT_DATA3             (SDMODE_DATA | 0x0001)#elif (BSPCONF_SDRAM_TYPE == SDRAM_TYPE_HY57V653220)/*                              32x1      32x1h  16x1   16x16 */#define SDMODE_DATA             0x1800 /* 0x9C00 0x5900 0x1900 */#define SDREF_DATA              0x0540 /* 0x0140 0x0140 0x0140 */#define SDCNT_DATA1             0x1002 /* 0x9C02 0x5902 0x1902 */#define SDCNT_DATA2             0x1004 /* 0x9C04 0x5904 0x1904 */#define SDCNT_DATA3             0x1001 /* 0x9C01 0x5901 0x1901 */#elif (BSPCONF_SDRAM_TYPE == SDRAM_TYPE_HY57V561620)/*                              32x1      32x1h  16x1   16x16 */