?? mb90460.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.4 */
/* DATE: 24.09.01 TIME: 11:45:36 */
/* */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0 (or higher)" */
/* see "\START.HTM" or see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 26-09-00 1.0 MST file created */
/* 06-10-00 1.1 MST Register bit name corrected */
/* 01.11.00 1.2 NMP ADC Structure realigned */
/* 08.11.00 1.3 NMP Rebuild to remove comments */
/* 20.04.01 1.4 MST Security section added */
/* 24.09.01 1.5 MST Bit name of DIVx register DIVx changed to Dx */
/* Bit name of CDCRx register DIVx changed to DVx */
.PROGRAM MB90460
.TITLE MB90460
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __pwcsl0, __pwcsh0, __pwc0, __div0, __ddr0
.GLOBAL __ddr1, __ddr2, __ddr3, __ddr4, __ddr5, __ddr6
.GLOBAL __ader, __cdcr0, __cdcr1, __rdr0, __rdr1, __smr0
.GLOBAL __scr0, __sidr0, __sodr0, __ssr0, __smr1, __scr1
.GLOBAL __sidr1, __sodr1, __ssr1, __pwcsl1, __pwcsh1, __pwc1
.GLOBAL __div1, __enir, __eirr, __elvr, __adcs, __adcs0
.GLOBAL __adcs1, __adcr, __adcr0, __adcr1, __pdcr0, __pdcrl0
.GLOBAL __pdcrh0, __pcsr0, __pcsrl0, __pcsrh0, __pdut0, __pdutl0
.GLOBAL __pduth0, __pcnt0, __pcntl0, __pcnth0, __pdcr1, __pdcrl1
.GLOBAL __pdcrh1, __pcsr1, __pcsrl1, __pcerh1, __pdut1, __pdutl1
.GLOBAL __pduth1, __pcnt1, __pcntl1, __pcnth1, __pdcr2, __pdcrl2
.GLOBAL __pdcrh2, __pcsr2, __pcsrl2, __pcsrh2, __pdut2, __pdutl2
.GLOBAL __pduth2, __pcnt2, __pcntl2, __pcnth2, __tmrr0, __tmrr1
.GLOBAL __tmrr2, __dtcr0, __dtcr1, __dtcr2, __sigcr, __cpclr
.GLOBAL __tcdt, __tccs, __tccsl, __tccsh, __ipcp0, __ipcp1
.GLOBAL __ipcp2, __ipcp3, __ics01, __icsl01, __icsh01, __ics23
.GLOBAL __ics23l, __ics23h, __romm, __occp0, __occp1, __occp2
.GLOBAL __occp3, __occp4, __occp5, __ocs0, __ocs1, __ocs2
.GLOBAL __ocs3, __ocs4, __ocs5, __tmcr0, __tmcsr0, __tmcr1
.GLOBAL __tmcsr1, __tmr0, __tmr0l, __tmr0h, __tmrlr0, __tmrlr0l
.GLOBAL __tmrlr0h, __tmr1, __tmr1l, __tmr1h, __tmrlr1, __tmrlr1l
.GLOBAL __tmrlr1h, __opcr, __opclr, __opcur, __ipcr, __ipclr
.GLOBAL __ipcur, __tcsr, __nccr, __pacsr, __dirr, __lpmcr
.GLOBAL __ckscr, __wdtc, __tbtc, __fmcs, __icr00, __icr01
.GLOBAL __icr02, __icr03, __icr04, __icr05, __icr06, __icr07
.GLOBAL __icr08, __icr09, __icr10, __icr11, __icr12, __icr13
.GLOBAL __icr14, __icr15
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
.org 0x0008
__pwcsl0 .res.b 1 ;000008 /* PWC0 */
PWCSL0 .equ 0x0008
__pwcsh0 .res.b 1 ;000009
PWCSH0 .equ 0x0009
__pwc0 .res.b 2 ;00000A
PWC0 .equ 0x000A
__div0 .res.b 1 ;00000C
DIV0 .equ 0x000C
.org 0x0010
__ddr0 .res.b 1 ;000010 /* PORT DIR */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ader .res.b 1 ;000017 /* Analog Input Enable Register */
ADER .equ 0x0017
.org 0x0019
__cdcr0 .res.b 1 ;000019
CDCR0 .equ 0x0019
.org 0x001B
__cdcr1 .res.b 1 ;00001B
CDCR1 .equ 0x001B
__rdr0 .res.b 1 ;00001C /* Port pull-up resistor setting register */
RDR0 .equ 0x001C
__rdr1 .res.b 1 ;00001D
RDR1 .equ 0x001D
.org 0x0020
__smr0 .res.b 1 ;000020 /* UART0,1 */
SMR0 .equ 0x0020
__scr0 .res.b 1 ;000021
SCR0 .equ 0x0021
__sidr0 .res.b 1 ;000022
SIDR0 .equ 0x0022
.org 0x0022
__sodr0 .res.b 1 ;000022
SODR0 .equ 0x0022
__ssr0 .res.b 1 ;000023
SSR0 .equ 0x0023
__smr1 .res.b 1 ;000024
SMR1 .equ 0x0024
__scr1 .res.b 1 ;000025
SCR1 .equ 0x0025
__sidr1 .res.b 1 ;000026
SIDR1 .equ 0x0026
.org 0x0026
__sodr1 .res.b 1 ;000026
SODR1 .equ 0x0026
__ssr1 .res.b 1 ;000027
SSR1 .equ 0x0027
__pwcsl1 .res.b 1 ;000028 /* PWC1 */
PWCSL1 .equ 0x0028
__pwcsh1 .res.b 1 ;000029
PWCSH1 .equ 0x0029
__pwc1 .res.b 2 ;00002A
PWC1 .equ 0x002A
__div1 .res.b 1 ;00002C
DIV1 .equ 0x002C
.org 0x0030
__enir .res.b 1 ;000030 /* DTP, External Interrupts */
ENIR .equ 0x0030
__eirr .res.b 1 ;000031
EIRR .equ 0x0031
__elvr .res.b 2 ;000032
ELVR .equ 0x0032
__adcs .res.b 2 ;000034 /* AD Converter */
ADCS .equ 0x0034
.org 0x0034
__adcs0 .res.b 1 ;000034
ADCS0 .equ 0x0034
__adcs1 .res.b 1 ;000035
ADCS1 .equ 0x0035
__adcr .res.b 2 ;000036
ADCR .equ 0x0036
.org 0x0036
__adcr0 .res.b 1 ;000036
ADCR0 .equ 0x0036
__adcr1 .res.b 1 ;000037
ADCR1 .equ 0x0037
__pdcr0 .res.b 2 ;000038 /* Puls Pattern Generator Channel 0 */
PDCR0 .equ 0x0038
.org 0x0038
__pdcrl0 .res.b 1 ;000038
PDCRL0 .equ 0x0038
__pdcrh0 .res.b 1 ;000039
PDCRH0 .equ 0x0039
__pcsr0 .res.b 2 ;00003A
PCSR0 .equ 0x003A
.org 0x003A
__pcsrl0 .res.b 1 ;00003A
PCSRL0 .equ 0x003A
__pcsrh0 .res.b 1 ;00003B
PCSRH0 .equ 0x003B
__pdut0 .res.b 2 ;00003C
PDUT0 .equ 0x003C
.org 0x003C
__pdutl0 .res.b 1 ;00003C
PDUTL0 .equ 0x003C
__pduth0 .res.b 1 ;00003D
PDUTH0 .equ 0x003D
__pcnt0 .res.b 2 ;00003E
PCNT0 .equ 0x003E
.org 0x003E
__pcntl0 .res.b 1 ;00003E
PCNTL0 .equ 0x003E
__pcnth0 .res.b 1 ;00003F
PCNTH0 .equ 0x003F
__pdcr1 .res.b 2 ;000040 /* Puls Pattern Generator Channel 1 */
PDCR1 .equ 0x0040
.org 0x0040
__pdcrl1 .res.b 1 ;000040
PDCRL1 .equ 0x0040
__pdcrh1 .res.b 1 ;000041
PDCRH1 .equ 0x0041
__pcsr1 .res.b 2 ;000042
PCSR1 .equ 0x0042
.org 0x0042
__pcsrl1 .res.b 1 ;000042
PCSRL1 .equ 0x0042
__pcerh1 .res.b 1 ;000043
PCERH1 .equ 0x0043
__pdut1 .res.b 2 ;000044
PDUT1 .equ 0x0044
.org 0x0044
__pdutl1 .res.b 1 ;000044
PDUTL1 .equ 0x0044
__pduth1 .res.b 1 ;000045
PDUTH1 .equ 0x0045
__pcnt1 .res.b 2 ;000046
PCNT1 .equ 0x0046
.org 0x0046
__pcntl1 .res.b 1 ;000046
PCNTL1 .equ 0x0046
__pcnth1 .res.b 1 ;000047
PCNTH1 .equ 0x0047
__pdcr2 .res.b 2 ;000048 /* Puls Pattern Generator Channel 2 */
PDCR2 .equ 0x0048
.org 0x0048
__pdcrl2 .res.b 1 ;000048
PDCRL2 .equ 0x0048
__pdcrh2 .res.b 1 ;000049
PDCRH2 .equ 0x0049
__pcsr2 .res.b 2 ;00004A
PCSR2 .equ 0x004A
.org 0x004A
__pcsrl2 .res.b 1 ;00004A
PCSRL2 .equ 0x004A
__pcsrh2 .res.b 1 ;00004B
PCSRH2 .equ 0x004B
__pdut2 .res.b 2 ;00004C
PDUT2 .equ 0x004C
.org 0x004C
__pdutl2 .res.b 1 ;00004C
PDUTL2 .equ 0x004C
__pduth2 .res.b 1 ;00004D
PDUTH2 .equ 0x004D
__pcnt2 .res.b 2 ;00004E
PCNT2 .equ 0x004E
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