/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.                                             */
/*                 (C) Fujitsu Microelectronics Europe GmbH                  */
/*------------------------------------------------------------------------
  ocu.C
  - description
  - See README.TXT for project description and disclaimer.

/*------------------------------------------------------------------------*/

#include "mb90460.h"

/* global variable */


/* Init Compare Control Register */
void InitCompareControlRegister01 (void)
{
OCS1_CMOD=1; /* Output level reverse mode */
/* init register 0 */
 
OCCP0=0xfff; /* write value into Compare register */

OCS1_OTE0=1; /* Output enable bit */
OCS1_OTD0=0; /* Output level bit */
OCS0_IOP0=0; /* Compare match interrupt flag bit */
OCS0_IOE0=0; /* Compare match interrupt enable bit */
OCS1_BTS0=1; /* buffer transfer select bit ('1'[default]: compare clear; '0':zero detect) */

/* ensure that value is written to conpare register before compare operation is enabled */ 
OCS0_CST0=1; /* Compare operation enable bit */

/* init register 1 */

OCCP1=0xff; /* write value into Compare register */ 

OCS1_OTE1=1; /* Output enable bit */
OCS1_OTD1=0; /* Output level bit */
OCS0_IOP1=0; /* Compare match interrupt flag bit */
OCS0_IOE1=1; /* Compare match interrupt enable bit */
OCS1_BTS1=1; /* buffer transfer select bit ('1'[default]: compare clear; '0':zero detect) */

/* ensure that value is written to conpare register before compare operation is enabled */ 
OCS0_CST1=1; /* Compare operation enable bit */
}


void InitCompareControlRegister23 (void)
{

OCS3_CMOD=1; /* Output level reverse mode */

/* init register 2 */

OCCP2=0xfff; /* write value into Compare register */ 

OCS3_OTE0=1; /* Output enable bit */
OCS3_OTD0=0; /* Output level bit */
OCS2_IOP0=0; /* Compare match interrupt flag bit */
OCS2_IOE0=0; /* Compare match interrupt enable bit */
OCS3_BTS0=1; /* buffer transfer select bit ('1'[default]: compare clear; '0':zero detect) */

/* ensure that value is written to compare register before compare operation is enabled */ 
OCS2_CST0=1; /* Compare operation enable bit */

/* init register 3 */
 
OCCP3=0x7ff; /* write value into Compare register */

OCS3_OTE1=1; /* Output enable bit */
OCS3_OTD1=0; /* Output level bit */
OCS2_IOP1=0; /* Compare match interrupt flag bit */
OCS2_IOE1=1; /* Compare match interrupt enable bit */
OCS3_BTS1=1; /* buffer transfer select bit ('1'[default]: compare clear; '0':zero detect) */

/* ensure that value is written to compare register before compare operation is enabled */ 
OCS2_CST1=1; /* Compare operation enable bit */
}


void InitCompareControlRegister45 (void)
{
OCS5_CMOD=1; /* Output level reverse mode */

/* init register 4 */
OCCP4=0xfff; /* write value into Compare register */ 
OCS5_OTE0=1; /* Output enable bit */
OCS5_OTD0=0; /* Output level bit */
OCS4_IOP0=0; /* Compare match interrupt flag bit */
OCS4_IOE0=0; /* Compare match interrupt enable bit */
OCS5_BTS0=1; /* buffer transfer select bit ('1'[default]: compare clear; '0':zero detect) */

/* ensure that value is written to compare register before compare operation is enabled */ 
OCS4_CST0=1; /* Compare operation enable bit */

/* init register 5 */
 
OCCP5=0x9ff; /* write value into Compare register */

OCS5_OTE1=1; /* Output enable bit */
OCS5_OTD1=0; /* Output level bit */
OCS4_IOP1=0; /* Compare match interrupt flag bit */
OCS4_IOE1=1; /* Compare match interrupt enable bit */
OCS5_BTS1=1; /* buffer transfer select bit ('1'[default]: compare clear; '0':zero detect) */


/* ensure that value is written to compare register before compare operation is enabled */ 
OCS4_CST1=1; /* Compare operation enable bit */
}


/* Init Free Running Timer */
void InitFreeRunningTimer (void)
{
	TCCS_ECKE=0;    	/* select internal clock */
	TCCS_IRQZF=0;   	/* zero detect interrupt request flag */
	TCCS_IRQZE=0;   	/* Zero detect interupt enable bit */
	TCCS_MSI2=0;    	/* masking interrupt bits MSI2-0 */
	TCCS_MSI1=0;    	/* when using compare clear or zero detect interrupt */
	TCCS_MSI0=0;    	/* in demo not used */
	TCCS_ICLR=0;    	/* compare clear interrupt request bit */
	TCCS_ICRE=0;    	/* enable compare clear interrupt */
  
	TCCS_BFE=0;			/* Compare clear buffer enable bit */ 

	TCCS_MODE=0;    	/* select counter mode (up ['0'default] or down ['1'] count) */
	TCCS_SCLR=1;    	/* clear counter to 0X0000  */
	TCCS_CLK2=0;    	/* Clock frequency selection bits CLK2-0 */
	TCCS_CLK1=0;    	/* ('000' internal clock, no pre-scaler') */
	TCCS_CLK0=0; 
 
  
	TCCS_STOP=0;    	/* Counter enable bit, setting to '1' stop counter*/

}




void main(void)
{
    int i;
    
    InitIrqLevels();
    InitCompareControlRegister01();
    InitCompareControlRegister23();
    InitCompareControlRegister45();
    InitFreeRunningTimer();

    __set_il(7);				/* allow all levels */
    __EI();						/* globaly enable interrupts */
    
    while (1)
    {
    i++;		/* dummy loop */
    }
    
}
/* End of main */


__interrupt void OutputCompare0 (void)
{

OCS0_IOP0 =0;    /* clear interrupt bit */
}

__interrupt void OutputCompare1 (void)
{
OCS0_IOP1 =0;    /* Clear interrupt bit */
}

__interrupt void OutputCompare2 (void)
{
OCS2_IOP1 =0;    /* Clear interrupt bit */
}

__interrupt void OutputCompare3 (void)
{
OCS2_IOP1 =0;    /* Clear interrupt bit */
}

__interrupt void OutputCompare4 (void)
{
OCS4_IOP0 =0;    /* Clear interrupt bit */
}

__interrupt void OutputCompare5 (void)
{
OCS4_IOP1 =0;    /* Clear interrupt bit */
}


__interrupt void FreeRunclear (void)
{
TCCS_ICLR = 0;  /* clear interrupt request bit */
}