-- Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
-- The files included in this design directory contain proprietary, confidential information of 
-- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied 
-- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. 
-- This copyright notice must be retained as part of this text at all times. 


Description: Gold Code Generators in Virtex Devices. For a full functional 
description see Application Note 217:  http://www.xilinx.com/xapp/xapp217.pdf


Design Type: ISE (chip V50 BG256 -6)

Source Files:

Files Hierarchy:
	infer.v (Top-level)
	sub_a.v (Implementation of one LFSR)
	sub_b.v (Implementation of second LFSR)

Inputs:
	Clock
	Enable
	Fill_En_A
	New_Fill_A
	Fill_En_B
	New_Fill_B
	
Outputs:
	Gold_Code

SIMULATION:
Requires the following simulation libraries:
	Unisims
	Simprims

Simulation Resolution must be set to PS.

Behavioural and RTL Simulation done using VHDL Testbench 
for each design.

Notes:
	- The sequence length can be configured by 
	  modifiying the parameters listed after the
	  module declaration in the sub_a.v and sub_b.v
	  files.
  	- The CLKDLL component is not inserted into the
	  code. To see how to use the CLKDLL in VHDL
	  see solution 5649 at http://support.xilinx.com


NOTE: If you are trying to run this example in a read-only location,    
the design hierachy will not display properly. Please copy the example  
project to a new location by using either Project Save As... from the File menu
pulldown in ISE or some other method of your choice. Copy the example to a location
where you have write permissions and the hiearchy will display properly. 

For support information and contacts please see:

	http://support.xilinx.com
or
	http://support.xilinx.com/support/services/contact_info.htm