`celldefinemodule nand4_b(y,a,b,c,d);input a,b,c,d;output y;nand (y, a, b, c, d);specify// Path Delays    (a,b,c,d => y) = 1.27;// Intrinsic characteristics that affect timing    specparam cell_area=385.12,           // layout area    	max_load$ = 0.5,		  // maximum load    	resistance$y=1.6, slope$y=0.2,  capacitance$=0.044;endspecifyendmodule`endcelldefine