?? monitor.sts
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#Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47
#Host
#ROUTING STATUS <<< F:/wenjian/第十一章/自動布線\plane.dsn >>>
Start Time: Report Time: Mon May 04 11:40:55 2009
Nets = 182 Connections = 572
Current Wire = 0 Reroute wires = 165
Completion = 84.62% Unconnections = 88
| ROUTING HISTORY ================================================================
| Pass | Conflicts | | | | | |Red| CPU Time |
| Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
| Filter | 1| 101| 6| 25| 62| 470| 0| 0| 0| 0:00:15| 0:00:15|
| Filter | 2| 11| 22| 44| 79| 532| 0| 0| 69| 0:00:06| 0:00:21|
| Center | 2| 0| 0| 0| 79| 506| 0| 0| | 0:00:00| 0:00:21|
| Miter | 2| 11| 21| 0| 79| 506| 0| 0| | 0:00:14| 0:00:35|
| Delete | 2| 0| 0| 0| 88| 486| 0| 0| | 0:00:00| 0:00:35|
| Conflicts between polygon wires and fixed objects: 0
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