\t (00:00:06) allegro 16.2 p005 (v16-2-57E) i86
\t (00:00:06) 

\t (00:00:06) Opening existing drawing...
\d (00:00:07) Database opened: F:/wenjian/第十一章/自動布線/Autorouted.brd
\t (00:00:07) Grids are drawn 400.00, 400.00 apart for enhanced viewability.
\i (00:00:07) trapsize 13029
\t (00:00:07) Grids are drawn 100.00, 100.00 apart for enhanced viewability.
\i (00:00:07) trapsize 11643
\i (00:00:07) trapsize 6981
\i (00:00:09) trapsize 6981
\i (00:00:10) generaledit 
\i (00:00:13) open 
\i (00:00:24) fillin "F:\wenjian\第十一章\快速擺放元件\placed.brd"
\i (00:00:24) cd "F:\wenjian\第十一章\快速擺放元件"
\t (00:00:24) Opening existing drawing...
\t (00:00:24) Grids are drawn 100.00, 100.00 apart for enhanced viewability.
\i (00:00:24) trapsize 8125
\d (00:00:24) Database opened: F:/wenjian/第十一章/快速擺放元件/placed.brd
\i (00:00:24) generaledit 
\i (00:00:27) zoom out 1 
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out 3184.42 3246.53
\t (00:00:27) Grids are drawn 400.00, 400.00 apart for enhanced viewability.
\i (00:00:27) trapsize 16251
\i (00:00:28) zoom in 1 
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom in 1095.21 1556.44
\t (00:00:28) Grids are drawn 100.00, 100.00 apart for enhanced viewability.
\i (00:00:28) trapsize 8125
\i (00:00:31) roam x -96 
\i (00:00:31) roam x -96
\i (00:00:32) roam y 96 
\i (00:00:32) roam y 96
\i (00:00:33) roam y -96 
\i (00:00:33) roam y -96
\i (00:00:39) save_as 
\i (00:01:17) fillin "menu_cancel"
\i (00:01:17) generaledit 
\i (00:01:30) unrats all 
\i (00:01:31) generaledit 
\i (00:01:33) save_as 
\i (00:02:12) fillin "F:\wenjian\第十二章\ft-placed.brd"
\i (00:02:12) cd "F:\wenjian\第十二章"
\i (00:02:12) generaledit 
\i (00:02:31) define grid 
\i (00:02:31) generaledit 
\i (00:02:41) setwindow form.grid
\i (00:02:41) FORM grid non_etch non_etch_x_grids 5.00 
\i (00:02:43) FORM grid non_etch non_etch_y_grids 5.00 
\i (00:02:44) FORM grid top subclass_x_grids 5.00 
\i (00:02:44) FORM grid done  
\i (00:03:11) setwindow form.vf_vis
\i (00:03:11) FORM vf_vis all_etch_visible_pln YES 
\i (00:03:12) FORM vf_vis all_via_visible_pln YES 
\i (00:03:12) FORM vf_vis all_pin_visible_pln YES 
\i (00:03:18) FORM vf_vis 1 all_colorvisible NO 
\i (00:03:21) FORM vf_vis 4 all_colorvisible NO 
\i (00:03:23) FORM vf_vis 5 all_colorvisible NO 
\i (00:03:25) FORM vf_vis 2 etch_colorvisible 0 
\i (00:03:26) FORM vf_vis 2 etch_colorvisible 1 
\i (00:03:29) FORM vf_vis 2 etch_colorvisible 0 
\i (00:03:29) FORM vf_vis 2 etch_colorvisible 1 
\i (00:03:45) setwindow pcb
\i (00:03:45) color192 
\i (00:03:46) setwindow cvf.dialog
\i (00:03:46) cvf layer_mode
\i (00:03:46) setwindow pcb
\i (00:03:46) generaledit 
\i (00:04:19) setwindow cvf.dialog
\i (00:04:19) cvf select_color_cell 8
\i (00:04:20) cvf layers_color stack-up pin/gnd 9
\i (00:04:21) cvf layers_color stack-up via/gnd 9
\i (00:04:24) cvf layers_color stack-up etch/gnd 9
\i (00:04:29) cvf select_color_cell 6
\i (00:04:30) cvf layers_color stack-up pin/vcc 7
\i (00:04:31) cvf layers_color stack-up via/vcc 7
\i (00:04:31) cvf layers_color stack-up etch/vcc 7
\i (00:04:47) cvf layer_tree_item 'Route KeepOut' 'Areas'
\i (00:04:52) cvf select_color_cell 8
\i (00:04:54) cvf layers_color areas route_keepout/gnd 9
\i (00:04:54) cvf layers_visible areas route_keepout/gnd TRUE
\i (00:04:57) cvf layers_visible areas route_keepout/vcc TRUE
\i (00:04:59) cvf select_color_cell 6
\i (00:04:59) cvf layers_color areas route_keepout/vcc 7
\i (00:05:12) cvf apply
\i (00:05:14) cvf okay
\i (00:05:32) setwindow pcb
\i (00:05:32) dehilight 
\i (00:05:44) setwindow form.mini
\i (00:05:44) FORM mini net  
\i (00:05:48) FORM mini subclass GND 
\t (00:05:48) Grids are drawn 80.00, 80.00 apart for enhanced viewability.
\i (00:05:58) FORM mini subclass VCC 
\t (00:05:58) Grids are drawn 100.00, 100.00 apart for enhanced viewability.
\i (00:06:40) setwindow pcb
\i (00:06:40) color192 
\i (00:06:48) setwindow cvf.dialog
\i (00:06:48) cvf select_color_cell 71
\i (00:06:50) cvf layers_color stack-up pin/gnd 72
\i (00:06:52) cvf layers_color stack-up via/gnd 72
\i (00:06:55) cvf layers_color stack-up etch/gnd 72
\i (00:06:57) cvf select_color_cell 16
\i (00:06:59) cvf layers_color stack-up pin/bottom 17
\i (00:06:59) cvf layers_color stack-up pin/bottom 17
\i (00:07:00) cvf layers_color stack-up pin/vcc 17
\i (00:07:01) cvf layers_color stack-up via/vcc 17
\i (00:07:01) cvf layers_color stack-up etch/vcc 17
\i (00:07:03) cvf select_color_cell 1
\i (00:07:04) cvf layers_color stack-up pin/bottom 2
\i (00:07:17) cvf layers_visible stack-up anti_etch/top FALSE
\i (00:07:45) cvf layer_tree_item 'Route KeepOut' 'Areas'
\i (00:07:58) cvf layer_tree_item 'Conductor' 'Stack-Up'
\i (00:08:01) cvf select_color_cell 8
\i (00:08:03) cvf layers_color stack-up pin/gnd 9
\i (00:08:03) cvf layers_color stack-up via/gnd 9
\i (00:08:04) cvf layers_color stack-up etch/gnd 9
\i (00:08:56) cvf layer_tree_item 'Route KeepOut' 'Areas'
\i (00:09:05) cvf select_color_cell 16
\i (00:09:06) cvf layers_color areas route_keepout/vcc 17
\i (00:09:08) cvf apply
\i (00:09:09) cvf okay
\i (00:09:11) setwindow pcb
\i (00:09:11) zoom out 1 
\i (00:09:11) setwindow pcb
\i (00:09:11) zoom out 2297.78 2951.58
\t (00:09:11) Grids are drawn 400.00, 400.00 apart for enhanced viewability.
\i (00:09:11) trapsize 16251
\i (00:09:12) zoom in 1 
\i (00:09:12) setwindow pcb
\i (00:09:12) zoom in 4540.39 1407.75
\t (00:09:12) Grids are drawn 100.00, 100.00 apart for enhanced viewability.
\i (00:09:12) trapsize 8125
\i (00:09:13) zoom in 1 
\i (00:09:13) setwindow pcb
\i (00:09:13) zoom in 3662.85 1456.51
\i (00:09:13) trapsize 4063
\i (00:09:14) zoom out 1 
\i (00:09:14) setwindow pcb
\i (00:09:14) zoom out 3662.85 1456.52
\i (00:09:14) trapsize 8125
\i (00:09:15) roam x -96 
\i (00:09:15) roam x -96
\i (00:09:16) roam x -96 
\i (00:09:16) roam x -96
\i (00:09:17) zoom in 1 
\i (00:09:17) setwindow pcb
\i (00:09:17) zoom in 835.21 1472.77
\i (00:09:17) trapsize 4063
\i (00:09:17) zoom in 1 
\i (00:09:17) setwindow pcb
\i (00:09:17) zoom in 835.21 1472.77
\i (00:09:17) trapsize 2031
\i (00:09:18) zoom out 1 
\i (00:09:18) setwindow pcb
\i (00:09:18) zoom out 835.21 1472.77
\i (00:09:18) trapsize 4063
\i (00:09:18) zoom out 1 
\i (00:09:18) setwindow pcb
\i (00:09:18) zoom out 835.22 1472.77
\i (00:09:18) trapsize 8125
\i (00:09:19) zoom in 1 
\i (00:09:19) setwindow pcb
\i (00:09:19) zoom in 835.22 1472.78
\i (00:09:19) trapsize 4063
\i (00:09:20) zoom out 1 
\i (00:09:20) setwindow pcb
\i (00:09:20) zoom out 802.72 1489.03
\i (00:09:20) trapsize 8125
\i (00:09:24) color192 
\i (00:09:29) setwindow cvf.dialog
\i (00:09:29) cvf layer_tree_item 'Package KeepOut' 'Areas'
\i (00:09:32) cvf layer_tree_item 'Package KeepIn' 'Areas'
\i (00:09:39) cvf select_color_cell 0
\i (00:09:41) cvf select_color_cell 1
\i (00:09:42) cvf layers_color areas package_keepin/through_all 2
\i (00:09:43) cvf apply
\i (00:09:54) cvf select_color_cell 13
\i (00:09:55) cvf layers_color areas package_keepin/through_all 14
\i (00:10:00) cvf select_color_cell 69
\i (00:10:01) cvf layers_color areas package_keepin/through_all 70
\i (00:10:04) cvf apply
\i (00:10:14) setwindow pcb
\i (00:10:14) save 
\f (00:10:14) F:/wenjian/第十二章/ft-placed.brd: File Exists. Overwrite? 
\i (00:10:17) fillin yes 
\i (00:10:17) generaledit 
\i (00:11:07) zoom in 1 
\i (00:11:07) setwindow pcb
\i (00:11:07) zoom in 3549.11 709.00
\i (00:11:07) trapsize 4063
\i (00:11:07) zoom in 1 
\i (00:11:07) setwindow pcb
\i (00:11:07) zoom in 3549.11 709.00
\i (00:11:07) trapsize 2031
\i (00:11:10) zoom in 1 
\i (00:11:10) setwindow pcb
\i (00:11:10) zoom in 3549.11 709.01
\i (00:11:10) trapsize 1016
\i (00:11:11) zoom out 1 
\i (00:11:11) setwindow pcb
\i (00:11:11) zoom out 3549.11 709.01
\i (00:11:11) trapsize 2031
\i (00:11:11) zoom out 1 
\i (00:11:11) setwindow pcb
\i (00:11:11) zoom out 3549.11 709.01
\i (00:11:11) trapsize 4063
\i (00:11:11) zoom out 1 
\i (00:11:11) setwindow pcb
\i (00:11:11) zoom out 3549.12 709.00
\i (00:11:11) trapsize 8125
\i (00:11:12) zoom in 1 
\i (00:11:12) setwindow pcb
\i (00:11:12) zoom in 2167.79 1017.77
\i (00:11:12) trapsize 4063
\i (00:11:12) zoom in 1 
\i (00:11:12) setwindow pcb
\i (00:11:12) zoom in 2167.79 1017.78
\i (00:11:12) trapsize 2031
\i (00:11:13) zoom out 1 
\i (00:11:13) setwindow pcb
\i (00:11:13) zoom out 2017.47 1103.09
\i (00:11:13) trapsize 4063
\i (00:11:13) zoom out 1 
\i (00:11:13) setwindow pcb
\i (00:11:13) zoom out 2017.48 1103.10
\i (00:11:13) trapsize 8125
\i (00:11:14) zoom in 1 
\i (00:11:14) setwindow pcb
\i (00:11:14) zoom in 652.39 1476.87
\i (00:11:14) trapsize 4063
\i (00:11:14) zoom in 1 
\i (00:11:14) setwindow pcb
\i (00:11:14) zoom in 644.26 1485.00
\i (00:11:14) trapsize 2031
\i (00:11:15) zoom out 1 
\i (00:11:15) setwindow pcb
\i (00:11:15) zoom out 644.26 1485.00
\i (00:11:15) trapsize 4063
\i (00:11:15) zoom out 1 
\i (00:11:15) setwindow pcb
\i (00:11:15) zoom out 644.26 1485.00
\i (00:11:15) trapsize 8125
\i (00:11:19) dehilight 
\i (00:11:35) setwindow form.mini
\i (00:11:35) FORM mini net  
\i (00:11:44) FORM mini subclass GND 
\t (00:11:44) Grids are drawn 80.00, 80.00 apart for enhanced viewability.
\i (00:11:46) FORM mini net  
\i (00:11:49) setwindow pcb
\i (00:11:49) color192 
\i (00:11:49) setwindow cvf.dialog
\i (00:11:49) cvf layer_mode
\i (00:11:57) cvf select_color_cell 1
\i (00:12:03) cvf select_color_cell 71
\i (00:12:04) cvf layers_color stack-up pin/bottom 72
\i (00:12:04) cvf layers_color stack-up via/bottom 72
\i (00:12:06) cvf layers_color stack-up etch/bottom 72
\i (00:12:07) cvf layers_color stack-up flow_plan/bottom 72
\i (00:12:20) cvf apply
\i (00:12:23) cvf okay
\i (00:12:27) setwindow form.vf_vis
\i (00:12:27) FORM vf_vis 4 all_colorvisible YES 
\i (00:12:28) FORM vf_vis 4 all_colorvisible NO 
\i (00:14:10) setwindow pcb
\i (00:14:10) shape add 
\i (00:14:22) setwindow form.mini
\i (00:14:22) FORM mini subclass VCC 
\t (00:14:22) Grids are drawn 100.00, 100.00 apart for enhanced viewability.
\i (00:14:31) FORM mini dyns_fill_type Static solid 
\i (00:14:37) FORM mini dyns_netname_list  
\f (00:14:37) Select a net.
\i (00:14:50) fillin "Vcc"
\t (00:14:50) Assigning selected shape to net: VCC
\i (00:16:00) setwindow pcb
\i (00:16:00) color192 
\i (00:16:51) setwindow cvf.dialog
\i (00:16:51) cvf select_color_cell 71
\i (00:16:52) cvf layers_color stack-up pin/gnd 72
\i (00:16:53) cvf layers_color stack-up via/gnd 72
\i (00:16:53) cvf layers_color stack-up etch/gnd 72
\i (00:16:56) cvf select_color_cell 6
\i (00:16:57) cvf layers_color stack-up pin/bottom 7
\i (00:16:58) cvf layers_color stack-up via/bottom 7
\i (00:16:58) cvf layers_color stack-up etch/bottom 7
\i (00:17:00) cvf select_color_cell 1
\i (00:17:01) cvf layers_color stack-up etch/top 2
\i (00:17:04) cvf select_color_cell 6
\i (00:17:05) cvf layers_color stack-up pin/vcc 7
\i (00:17:06) cvf layers_color stack-up via/vcc 7
\i (00:17:06) cvf layers_color stack-up etch/vcc 7
\i (00:17:20) cvf select_color_cell 8
\i (00:17:21) cvf layers_color stack-up pin/bottom 9
\i (00:17:21) cvf layers_color stack-up via/bottom 9
\i (00:17:22) cvf layers_color stack-up etch/bottom 9
\i (00:17:35) cvf apply
\i (00:17:45) cvf okay
\i (00:17:49) setwindow form.vf_vis
\i (00:17:49) FORM vf_vis 1 all_colorvisible YES 
\i (00:17:51) FORM vf_vis 4 all_colorvisible YES 
\i (00:17:54) setwindow pcb
\i (00:17:54) zoom in 1 
\i (00:17:54) setwindow pcb
\i (00:17:54) zoom in 2789.38 1875.03
\i (00:17:54) trapsize 4063
\i (00:17:54) zoom in 1 
\i (00:17:54) setwindow pcb
\i (00:17:54) zoom in 2789.38 1875.03
\i (00:17:54) trapsize 2031
\i (00:17:55) zoom out 1 
\i (00:17:55) setwindow pcb
\i (00:17:55) zoom out 2789.38 1879.10
\i (00:17:55) trapsize 4063
\i (00:17:55) zoom out 1 
\i (00:17:55) setwindow pcb
\i (00:17:55) zoom out 2789.38 1879.10
\i (00:17:55) trapsize 8125
\i (00:17:57) zoom in 1 
\i (00:17:57) setwindow pcb
\i (00:17:57) zoom in 2789.38 1895.35
\i (00:17:57) trapsize 4063
\i (00:18:02) zoom out 1 
\i (00:18:02) setwindow pcb
\i (00:18:02) zoom out 2748.75 1895.35
\i (00:18:02) trapsize 8125
\i (00:18:03) zoom in 1 
\i (00:18:03) setwindow pcb
\i (00:18:03) zoom in 2586.24 1895.36
\i (00:18:03) trapsize 4063
\i (00:18:03) zoom in 1 
\i (00:18:03) setwindow pcb
\i (00:18:03) zoom in 2586.24 1895.36
\i (00:18:03) trapsize 2031
\i (00:18:04) zoom in 1 
\i (00:18:04) setwindow pcb
\i (00:18:04) zoom in 2565.92 1895.36
\i (00:18:04) trapsize 1016
\i (00:18:05) zoom out 1 
\i (00:18:05) setwindow pcb
\i (00:18:05) zoom out 2565.92 1895.36
\i (00:18:05) trapsize 2031
\i (00:18:05) zoom out 1 
\i (00:18:05) setwindow pcb
\i (00:18:05) zoom out 2565.92 1895.36
\i (00:18:05) trapsize 4063
\i (00:18:06) zoom out 1 
\i (00:18:06) setwindow pcb
\i (00:18:06) zoom out 2565.93 1895.36
\i (00:18:06) trapsize 8125
\i (00:18:20) color192 
\i (00:18:23) setwindow cvf.dialog
\i (00:18:23) cvf select_color_cell 25
\i (00:18:24) cvf layers_color stack-up pin/bottom 26
\i (00:18:25) cvf layers_color stack-up via/bottom 26
\i (00:18:25) cvf layers_color stack-up etch/bottom 26
\i (00:18:28) cvf apply
\i (00:18:29) cvf okay
\i (00:18:31) setwindow pcb
\i (00:18:31) zoom in 1 
\i (00:18:31) setwindow pcb
\i (00:18:31) zoom in 3118.46 1424.09
\i (00:18:31) trapsize 4063
\i (00:18:31) zoom in 1 
\i (00:18:31) setwindow pcb
\i (00:18:31) zoom in 3118.46 1424.09
\i (00:18:31) trapsize 2031
\i (00:18:32) zoom out 1 
\i (00:18:32) setwindow pcb
\i (00:18:32) zoom out 3118.46 1424.09
\i (00:18:32) trapsize 4063
\i (00:18:32) zoom out 1 
\i (00:18:32) setwindow pcb
\i (00:18:32) zoom out 3118.46 1424.09
\i (00:18:32) trapsize 8125
\i (00:18:36) trapsize 6810
\i (00:18:42) setwindow form.vf_vis
\i (00:18:42) FORM vf_vis 1 all_colorvisible NO 
\i (00:18:45) FORM vf_vis 4 all_colorvisible NO 
\i (00:19:52) setwindow pcb
\i (00:19:52) color192 
\i (00:19:53) setwindow cvf.dialog
\i (00:19:53) cvf layer_tree_item 'Areas'
\i (00:19:57) cvf layer_tree_item 'Route KeepOut' 'Areas'
\i (00:20:01) cvf select_color_cell 71
\i (00:20:03) cvf layers_color areas route_keepout/gnd 72
\i (00:20:05) cvf select_color_cell 6
\i (00:20:06) cvf layers_color areas route_keepout/vcc 7
\i (00:20:09) cvf apply
\i (00:20:11) cvf okay
\i (00:20:13) setwindow pcb
\i (00:20:13) zoom in 1 
\i (00:20:13) setwindow pcb
\i (00:20:13) zoom in 38.29 649.87
\i (00:20:13) trapsize 3405
\i (00:20:14) zoom in 1 
\i (00:20:14) setwindow pcb
\i (00:20:14) zoom in 38.29 649.87
\i (00:20:14) trapsize 1702
\i (00:20:14) zoom out 1 
\i (00:20:14) setwindow pcb
\i (00:20:14) zoom out 34.88 646.47
\i (00:20:14) trapsize 3405
\i (00:20:14) zoom out 1 
\i (00:20:14) setwindow pcb
\i (00:20:14) zoom out 34.89 646.46
\i (00:20:14) trapsize 6810
\i (00:20:16) zoom out 1 
\i (00:20:16) setwindow pcb
\i (00:20:16) zoom out 116.61 714.57
\t (00:20:16) Grids are drawn 400.00, 400.00 apart for enhanced viewability.