# Cadence Design Systems, Inc.
# Allegro PCB Router Automatic Router
# Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47
# Running on host 
# 
#            Command Line Parameters
#            -----------------------
# Design File Name : F:/wenjian/第十一章/快速擺放元件\placed.dsn
# Initialization options:
#   -do pasde.do
# Status File Name : F:/wenjian/第十一章/快速擺放元件\monitor.sts
# -nog specified. Graphics not utilized.
# Use Colormap In Design File.
#
#
#
#
# do $/placed_rules.do
define (class '_difpr_DP-D1' D13 D10 )
define (class BA BA0 BA1 BA2 BA3 
  BA4 BA5 BA6 BA7 )
define (class BD BD0 BD1 BD2 BD3 
  BD4 BD5 BD6 BD7 
  BD8 BD9 BD10 BD11 
  BD12 BD13 BD14 BD15 )
define (class '_difpr_DP-BA' BA3 BA0 )
define (class _difpr_DP1 N16748 N16740 )
define (class '_difpr_DP-BD' BD3 BD0 )
define (class RA RA6 RA7 RA2 RA3 
  RA0 RA1 RA11 RA9 
  RA5 RA8 RA15 RA4 
  RA13 RA12 RA10 RA14 )
define (class RD RD0 RD1 RD2 RD3 
  RD4 RD6 RD5 RD7 )
define (class VD VD0 VD1 VD2 VD3 
  VD4 VD5 VD6 VD7 )
define (class '_difpr_DP-RA' RA0 RA3 )
define (class '_difpr_DP-RD' RD0 RD3 )
define (class '_difpr_DP-VD' VD3 VD0 )
define (class SYNC VCLKC VCLKA )
define (class A AEN AGND A0 A1 
  A2 A3 A4 A5 
  A6 A7 A8 A9 
  A10 A11 A12 A13 
  A14 A15 A16 A17 
  A18 A19 A20 A21 
  A22 A23 )
define (class '_difpr_DP-BD1' BD13 BD10 )
define (class D D0 D1 D2 D3 
  D4 D5 D6 D7 
  D8 D9 D10 D11 
  D12 D13 D14 D15 )
define (class '_difpr_DP-A' A3 A0 )
define (class '_difpr_DP-RA1' RA10 RA13 )
define (class '_difpr_DP-D' D3 D0 )
define (class '_difpr_DP-Q' Q0 Q3 )
define (class '_difpr_DP-RCS' RCS0 RCS3 )
define (class '_difpr_DP-A1' A13 A10 )
define (class '_difpr_DP-A2' A23 A20 )
define (pair (nets VD0 VD3 ))
define (pair (nets RD3 RD0 ))
define (pair (nets RA3 RA0 ))
define (pair (nets BD0 BD3 ))
define (pair (nets N16740 N16748 ))
define (pair (nets BA0 BA3 ))
define (pair (nets D10 D13 ))
define (pair (nets A20 A23 ))
define (pair (nets A10 A13 ))
define (pair (nets RCS3 RCS0 ))
define (pair (nets Q3 Q0 ))
define (pair (nets D0 D3 ))
define (pair (nets RA13 RA10 ))
define (pair (nets A0 A3 ))
define (pair (nets BD10 BD13 ))
rule PCB (width 6)
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 6 (type wire_wire))
rule PCB (clearance 6 (type wire_smd))
rule PCB (clearance 6 (type wire_pin))
rule PCB (clearance 6 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 6 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 6 (type pin_via))
rule PCB (clearance 6 (type via_via))
rule PCB (clearance 6 (type test_test))
rule PCB (clearance 6 (type test_wire))
rule PCB (clearance 6 (type test_smd))
rule PCB (clearance 6 (type test_pin))
rule PCB (clearance 6 (type test_via))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule PCB (clearance 6 (type microvia_microvia))
set microvia_microvia off
rule PCB (clearance 6 (type microvia_thrupin))
set microvia_thrupin off
rule PCB (clearance 6 (type microvia_smdpin))
set microvia_smdpin off
rule PCB (clearance 6 (type microvia_thruvia))
set microvia_thruvia off
rule PCB (clearance 6 (type microvia_bbvia))
set microvia_bbvia off
rule PCB (clearance 6 (type microvia_wire))
set microvia_wire off
rule PCB (clearance 6 (type microvia_testpin))
set microvia_testpin off
rule PCB (clearance 6 (type microvia_testvia))
set microvia_testvia off
rule PCB (clearance 6 (type microvia_bondpad))
set microvia_bondpad off
rule PCB (clearance 6 (type microvia_area))
set microvia_area off
rule PCB (clearance 6 (type nhole_pin))
set nhole_pin on
rule PCB (clearance 6 (type nhole_via))
set nhole_via on
rule PCB (clearance 6 (type nhole_wire))
set nhole_wire on
rule PCB (clearance 6 (type nhole_area))
set nhole_area on
rule PCB (clearance 6 (type nhole_nhole))
set nhole_nhole on
rule PCB (clearance 0 (type mhole_pin))
set mhole_pin on
rule PCB (clearance 0 (type mhole_via))
set mhole_via on
rule PCB (clearance 0 (type mhole_wire))
set mhole_wire on
rule PCB (clearance 0 (type mhole_area))
set mhole_area on
rule PCB (clearance 0 (type mhole_nhole))
set mhole_nhole on
rule PCB (clearance 0 (type mhole_mhole))
set mhole_mhole on
rule class SYNC (width 8)
rule class SYNC (clearance 8 (type wire_wire))
rule class SYNC (clearance 8 (type wire_smd))
rule class SYNC (clearance 8 (type wire_pin))
rule class SYNC (clearance 8 (type wire_via))
rule class SYNC (clearance 8 (type smd_smd))
rule class SYNC (clearance 8 (type smd_pin))
rule class SYNC (clearance 8 (type smd_via))
rule class SYNC (clearance 8 (type pin_pin))
rule class SYNC (clearance 8 (type pin_via))
rule class SYNC (clearance 8 (type via_via))
rule class SYNC (clearance 8 (type test_test))
rule class SYNC (clearance 8 (type test_wire))
rule class SYNC (clearance 8 (type test_smd))
rule class SYNC (clearance 8 (type test_pin))
rule class SYNC (clearance 8 (type test_via))
rule class SYNC (clearance 8 (type microvia_microvia))
rule class SYNC (clearance 8 (type microvia_thrupin))
rule class SYNC (clearance 8 (type microvia_smdpin))
rule class SYNC (clearance 8 (type microvia_thruvia))
rule class SYNC (clearance 8 (type microvia_bbvia))
rule class SYNC (clearance 8 (type microvia_wire))
rule class SYNC (clearance 8 (type microvia_testpin))
rule class SYNC (clearance 8 (type microvia_testvia))
rule class SYNC (clearance 8 (type microvia_bondpad))
rule class SYNC (clearance 8 (type microvia_area))
rule class SYNC (clearance 8 (type nhole_pin))
rule class SYNC (clearance 8 (type nhole_via))
rule class SYNC (clearance 8 (type nhole_wire))
rule class SYNC (clearance 8 (type nhole_area))
rule class SYNC (clearance 8 (type nhole_nhole))
rule net V12N (width 15)
rule net AGND (width 15)
rule net V12P (width 15)
rule net GND_EARTH (width 15)
rule net VCC (width 15)
rule class_class SYNC SYNC (clearance 5 (type buried_via_gap))
rule class_class SYNC SYNC (clearance 8 (type wire_wire))
rule class_class SYNC SYNC (clearance 8 (type wire_smd))
rule class_class SYNC SYNC (clearance 8 (type wire_pin))
rule class_class SYNC SYNC (clearance 8 (type wire_via))
rule class_class SYNC SYNC (clearance 8 (type smd_smd))
rule class_class SYNC SYNC (clearance 8 (type smd_pin))
rule class_class SYNC SYNC (clearance 8 (type smd_via))
rule class_class SYNC SYNC (clearance 8 (type pin_pin))
rule class_class SYNC SYNC (clearance 8 (type pin_via))
rule class_class SYNC SYNC (clearance 8 (type via_via))
rule class_class SYNC SYNC (clearance 8 (type test_test))
rule class_class SYNC SYNC (clearance 8 (type test_wire))
rule class_class SYNC SYNC (clearance 8 (type test_smd))
rule class_class SYNC SYNC (clearance 8 (type test_pin))
rule class_class SYNC SYNC (clearance 8 (type test_via))
rule class_class SYNC SYNC (clearance 8 (type microvia_microvia))
rule class_class SYNC SYNC (clearance 8 (type microvia_thrupin))
rule class_class SYNC SYNC (clearance 8 (type microvia_smdpin))
rule class_class SYNC SYNC (clearance 8 (type microvia_thruvia))
rule class_class SYNC SYNC (clearance 8 (type microvia_bbvia))
rule class_class SYNC SYNC (clearance 8 (type microvia_wire))
rule class_class SYNC SYNC (clearance 8 (type microvia_testpin))
rule class_class SYNC SYNC (clearance 8 (type microvia_testvia))
rule class_class SYNC SYNC (clearance 8 (type microvia_bondpad))
rule class_class SYNC SYNC (clearance 8 (type microvia_area))
rule class_class SYNC SYNC (clearance 8 (type nhole_pin))
rule class_class SYNC SYNC (clearance 8 (type nhole_via))
rule class_class SYNC SYNC (clearance 8 (type nhole_wire))
rule class_class SYNC SYNC (clearance 8 (type nhole_area))
rule class_class SYNC SYNC (clearance 8 (type nhole_nhole))
rule PCB (clearance -1 same_net (type wire_wire))
rule PCB (clearance -1 same_net (type wire_smd))
rule PCB (clearance -1 same_net (type wire_pin))