WARNING: There are no voltage nets defined in this design.
INFO: Using default signal_icnlibs = [interconn.iml cds_interconn.iml *.iml]
INFO: Loaded existing Interconnect file 'E:/Cadence/PCB圖的導入、放置和相關處理/interconn.iml'
INFO: Loaded existing Interconnect file 'C:/Cadence/SPB_16.2/share/pcb/signal/cds_interconn.iml'
INFO: Finished loading SigNoise interconnect libraries
INFO: Using working interconnect library 'E:/Cadence/PCB圖的導入、放置和相關處理/interconn.iml'
INFO: Field Solver bem2d for STL_0S_1R_1
INFO: Executing command: bem2d 0 "C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaaq03104.in" 0.00127
INFO: 2 non-encrypted models saved to file E:/Cadence/PCB圖的導入、放置和相關處理/sigxp.dml
INFO: 2 models saved in sigxp.dml