?? u盤電路設計.drc
字號:
Protel Design System Design Rule Check
PCB File : \Protel DXP 2004\Design\chapter13\U盤電路設計.PCBDOC
Date : 2005-5-22
Time : 16:21:22
Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.3mm) (InNet('VCC') Or InNet('VUSB') Or InNet('GND'))
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.2mm) (All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:00:05
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