*/#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control		11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR	(PISCR_PS | PISCR_PITF)/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */#define CFG_PLPRCR							\		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )#else			/* up to 66 MHz we use a 1:1 clock */#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)#endif	/* CONFIG_80MHz *//*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register		15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */#define SCCR_MASK	SCCR_EBDF11#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */#define CFG_SCCR	(/* SCCR_TBS  | */ \			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \			 SCCR_DFALCD00)#else			/* up to 66 MHz we use a 1:1 clock */#define CFG_SCCR	(SCCR_TBS     | \			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \			 SCCR_DFALCD00)#endif	/* CONFIG_80MHz *//*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- * */#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )#define CFG_PCMCIA_IO_ADDR	(0xEC000000)#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )/*----------------------------------------------------------------------- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) *----------------------------------------------------------------------- */#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/#define CFG_ATA_IDE0_OFFSET	0x0000#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR/* Offset for data I/O			*/#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)/* Offset for normal register accesses	*/#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)/* Offset for alternate registers	*/#define CFG_ATA_ALT_OFFSET	0x0100/*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */#define CFG_DER	0/* * Init Memory Controller: * * BR0/1 and OR0/1 (FLASH) */#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*//* used to re-map FLASH both when starting from SRAM or FLASH: * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask *//* * FLASH timing: */#if   defined(CONFIG_80MHz)/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \				 OR_SCY_3_CLK | OR_EHTR | OR_BI)#elif defined(CONFIG_66MHz)/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \				 OR_SCY_3_CLK | OR_EHTR | OR_BI)#else		/*   50 MHz *//* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \				 OR_SCY_2_CLK | OR_EHTR | OR_BI)#endif	/*CONFIG_??MHz */#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )#define CFG_OR1_REMAP	CFG_OR0_REMAP#define CFG_OR1_PRELIM	CFG_OR0_PRELIM#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )/* * BR2/3 and OR2/3 (SDRAM) * */#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*//* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/#define CFG_OR_TIMING_SDRAM	0x00000A00#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )#ifndef	CONFIG_CAN_DRIVER#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \					BR_PS_8 | BR_MS_UPMB | BR_V )#endif	/* CONFIG_CAN_DRIVER *//* * Memory Periodic Timer Prescaler * * The Divider for PTA (refresh timer) configuration is based on an * example SDRAM configuration (64 MBit, one bank). The adjustment to * the number of chip selects (NCS) and the actually needed refresh * rate is done by setting MPTPR. * * PTA is calculated from *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) * *	gclk	  CPU clock (not bus clock!) *	Trefresh  Refresh cycle * 4 (four word bursts used) * * 4096  Rows from SDRAM example configuration * 1000  factor s -> ms *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration *    4  Number of refresh cycles per period *   64  Refresh cycle in ms per number of rows * -------------------------------------------- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 * * 50 MHz => 50.000.000 / Divider =  98 * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */#if   defined(CONFIG_80MHz)#define CFG_MAMR_PTA		156#elif defined(CONFIG_66MHz)#define CFG_MAMR_PTA		129#else		/*   50 MHz */#define CFG_MAMR_PTA		 98#endif	/*CONFIG_??MHz *//* * For 16 MBit, refresh rates could be 31.3 us * (= 64 ms / 2K = 125 / quad bursts). * For a simpler initialization, 15.6 us is used instead. * * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank */#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*//* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*//* * MAMR settings for SDRAM *//* 8 column SDRAM */#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)/* 9 column SDRAM */#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)/* * Internal Definitions * * Boot Flags */#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*/#define CONFIG_SCC1_ENET#define CONFIG_FEC_ENET#define CONFIG_ETHPRIME		"SCC ETHERNET"#endif	/* __CONFIG_H */