/* * U-Boot configuration for SIXNET SXNI855T CPU board. * This board is based (loosely) on the Motorola FADS board, so this * file is based (loosely) on config_FADS860T.h, see it for additional * credits. * * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * *//* * Memory map: * *   ff100000 -> ff13ffff : FPGA        CS1 *   ff030000 -> ff03ffff : EXPANSION   CS7 *   ff020000 -> ff02ffff : DATA FLASH  CS4 *   ff018000 -> ff01ffff : UART B      CS6/UPMB *   ff010000 -> ff017fff : UART A      CS5/UPMB *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB *//* ------------------------------------------------------------------------- *//* * board/config.h - configuration options, board specific */#ifndef __CONFIG_H#define __CONFIG_H/* * High Level Configuration Options * (easy to change) */#include <mpc8xx_irq.h>#define CONFIG_SXNI855T		1	/* SIXNET IPm 855T CPU module *//* The 855T is just a stripped 860T and needs code for 860, so for now * at least define 860, 860T and 855T */#define CONFIG_MPC860		1#define CONFIG_MPC860T		1#define CONFIG_MPC855T		1#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/#undef	CONFIG_8xx_CONS_SMC2#undef	CONFIG_8xx_CONS_SCC1#undef	CONFIG_8xx_CONS_NONE#define CONFIG_BAUDRATE		9600#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/#define MPC8XX_FACT		10	/* 50 MHz is 5 MHz in times 10	*/#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */#if 0#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/#else#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/#endif/*----------------------------------------------------------------------- * Definitions for status LED */#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/# define STATUS_LED_PAR		im_ioport.iop_papar# define STATUS_LED_DIR		im_ioport.iop_padir# define STATUS_LED_ODR		im_ioport.iop_paodr# define STATUS_LED_DAT		im_ioport.iop_padat# define STATUS_LED_BIT		0x8000		/* LED 0 is on PA.0 */# define STATUS_LED_PERIOD	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */# define STATUS_LED_STATE	STATUS_LED_BLINKING# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */#ifdef DEV	/* development (debug) settings */#define CONFIG_BOOT_LED_STATE	STATUS_LED_OFF#else		/* production settings */#define CONFIG_BOOT_LED_STATE	STATUS_LED_ON#endif#define CONFIG_SHOW_BOOT_PROGRESS 1#define CONFIG_BOOTCOMMAND	"bootm f8040000 f8100000" /* autoboot command */#define CONFIG_BOOTARGS		"root=/dev/ram ip=off"#define CONFIG_MISC_INIT_R		/* have misc_init_r() function */#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/#define	CONFIG_RTC_DS1306		/* Dallas 1306 real time clock	*/#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*//* * Software (bit-bang) I2C driver configuration */#define PB_SCL		0x00000020	/* PB 26 */#define PB_SDA		0x00000010	/* PB 27 */#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \			else    immr->im_cpm.cp_pbdat &= ~PB_SDA#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \			else    immr->im_cpm.cp_pbdat &= ~PB_SCL#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */# define CFG_I2C_SPEED		50000# define CFG_I2C_SLAVE		0xFE# define CFG_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/# define CFG_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */#define CFG_DISCOVER_PHY#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		| \				 CFG_CMD_EEPROM		| \				 CFG_CMD_JFFS2		| \				 CFG_CMD_NAND		| \				 CFG_CMD_DATE)/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>#define CFG_JFFS_CUSTOM_PART#define CFG_JFFS2_SORT_FRAGMENTS/* JFFS2 location when using NOR flash */#define CFG_JFFS2_BASE	(CFG_FLASH_BASE + 0x80000)#define CFG_JFFS2_SIZE	(0x780000)/* JFFS2 location (in RAM) when using NAND flash */#define	CFG_JFFS2_RAMBASE 0x400000#define	CFG_JFFS2_RAMSIZE 0x200000	/* NAND boot partition is 2MiB	*//* NAND flash support */#define CONFIG_MTD_NAND_ECC_JFFS2#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/#define SECTORSIZE 512#define ADDR_COLUMN 1#define ADDR_PAGE 2#define ADDR_COLUMN_PAGE 3#define NAND_ChipID_UNKNOWN 	0x00#define NAND_MAX_FLOORS 1#define NAND_MAX_CHIPS 1/* DFBUSY is available on Port C, bit 12; 0 if busy */#define NAND_WAIT_READY(nand)	\	while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))#define WRITE_NAND(d, adr)	\	 do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)#define READ_NAND(adr) (*(volatile uint8_t *)(adr))#define	CLE_LO	0x01	/* 0 selects CLE mode (CLE high) */#define	ALE_LO	0x02	/* 0 selects ALE mode (ALE high) */#define	CE_LO	0x04	/* 1 selects chip (CE low) */#define	nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)#define NAND_DISABLE_CE(nand) \	nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)#define NAND_ENABLE_CE(nand) \	nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)#define NAND_CTL_CLRALE(nandptr) \	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)#define NAND_CTL_SETALE(nandptr) \	nand_setcr((nandptr) + 1, CE_LO | CLE_LO)#define NAND_CTL_CLRCLE(nandptr) \	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)#define NAND_CTL_SETCLE(nandptr) \	nand_setcr((nandptr) + 1, CE_LO | ALE_LO)/* * Miscellaneous configurable options */#define	CFG_LONGHELP			/* undef to save a little memory */#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/#else#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/#endif#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define	CFG_MAXARGS	16		/* max number of command args	*/#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/#define CFG_LOAD_ADDR	 	0x00100000