#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }/* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. *//*----------------------------------------------------------------------- * Internal Memory Mapped Register */#define CFG_IMMR		0xFF000000#define CFG_IMMR_SIZE		((uint)(64 * 1024))/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */#define CFG_INIT_RAM_ADDR	CFG_IMMR#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */#define	CFG_SDRAM_BASE		0x00000000#define	CFG_SRAM_BASE		0xF4000000#define	CFG_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */#define CFG_FLASH_BASE		0xF8000000#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */#define CFG_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */#define CFG_DFLASH_SIZE		0x00010000#define CFG_FPGA_BASE		0xFF100000	/* Xilinx FPGA */#define CFG_FPGA_PROG		0xFF130000	/* Programming address */#define CFG_FPGA_SIZE		0x00040000	/* 256KiB usable */#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/#define CFG_MONITOR_BASE	CFG_FLASH_BASE#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*//*----------------------------------------------------------------------- * FLASH organization */#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*//* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. * AMD 29LV641 has 128 64K sectors in 8MB */#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/#endif/*----------------------------------------------------------------------- * SYPCR - System Protection Control					11-9 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)#else#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)#endif/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration					11-6 *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)/*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control					11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control		11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR	(PISCR_PS | PISCR_PITF)/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30 *----------------------------------------------------------------------- * set the PLL, the low-power modes and the reset control (15-29) */#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)/*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register		15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */#define SCCR_MASK	SCCR_EBDF11#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */#define CFG_DER		0/* Because of the way the 860 starts up and assigns CS0 the * entire address space, we have to set the memory controller * differently.  Normally, you write the option register * first, and then enable the chip select by writing the * base register.  For CS0, you must write the base register * first, followed by the option register. *//* * Init Memory Controller: * ********************************************************** * BR0 and OR0 (FLASH) */#define CFG_PRELIM_OR0_AM	0xFC000000	/* OR addr mask *//* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)#define CFG_OR0_PRELIM	(CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)#define CONFIG_FLASH_16BIT#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )#define CFG_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware *//********************************************************** * BR1 and OR1 (FPGA) * These preliminary values are also the final values. */#define CFG_OR_TIMING_FPGA \	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)#define CFG_BR1_PRELIM	((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )#define CFG_OR1_PRELIM	(((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)/********************************************************** * BR4 and OR4 (data flash) * These preliminary values are also the final values. */#define CFG_OR_TIMING_DFLASH \	(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)#define CFG_BR4_PRELIM	((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )#define CFG_OR4_PRELIM	(((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)/********************************************************** * BR5/6 and OR5/6 (Dual UART) */#define CFG_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */#define CFG_DUARTA_BASE	0xff010000#define CFG_DUARTB_BASE	0xff018000#define DUART_MBMR	0#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)/********************************************************** * * Boot Flags */#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*/#define CONFIG_RESET_ON_PANIC		/* reset if system panic() */#define CFG_ENV_IS_IN_FLASH#ifdef CFG_ENV_IS_IN_FLASH  /* environment is in FLASH */  #define CFG_ENV_ADDR		0xF8040000	/* AM29LV641 or AM29LV800BT */  #define CFG_ENV_ADDR_REDUND	0xF8050000	/* AM29LV641 or AM29LV800BT */  #define CFG_ENV_SECT_SIZE	0x00010000  #define CFG_ENV_SIZE		0x00002000#else  /* environment is in EEPROM */  #define CFG_ENV_IS_IN_EEPROM		1  #define CFG_ENV_OFFSET		0	/* at beginning of EEPROM */  #define CFG_ENV_SIZE		     1024	/* Use only a part of it*/#endif#if 1#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"#define CONFIG_AUTOBOOT_DELAY_STR	"delayabit"#define CONFIG_AUTOBOOT_STOP_STR	" " /* easy to stop for now */#endif#endif	/* __CONFIG_H */