*/#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)/*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register		11-27 *----------------------------------------------------------------------- *//*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */#define CFG_RTCSC	(RTCSC_SEC |  RTCSC_ALR | RTCSC_RTE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control		11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! *//* up to 50 MHz we use a 1:1 clock */#define CFG_PLPRCR	( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)/*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register		15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */#define SCCR_MASK	SCCR_EBDF00/* up to 50 MHz we use a 1:1 clock */#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)/*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- * */#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )#define CFG_PCMCIA_IO_ADDR	(0xEC000000)#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )/*----------------------------------------------------------------------- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) *----------------------------------------------------------------------- */#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/#define CFG_ATA_IDE0_OFFSET	0x0000#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR/* Offset for data I/O			*/#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)/* Offset for normal register accesses	*/#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)/* Offset for alternate registers	*/#define CFG_ATA_ALT_OFFSET	0x0100/*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * *//* #define	CFG_DER	0x2002000F */#define CFG_DER	0/* * Init Memory Controller: * * BR0 and OR0 (FLASH) */#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask *//* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)/* * BR1 and OR1 (SDRAM) * */#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB *//* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/#define CFG_OR_TIMING_SDRAM	0x00000E00#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )/* RPXLITE mem setting */#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */#define CFG_OR3_PRELIM	0xff7f8970#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */#define CFG_OR4_PRELIM	0xFFF80970/* ECCX CS settings                                                          */#define SED13806_OR             0xFFC00108     /* - 4 Mo						   - Burst inhibit						   - external TA             */#define SED13806_REG_ADDR       0xa0000000#define SED13806_ACCES          0x801           /* 16 bit access             *//* Global definitions for the ECCX board                                     */#define ECCX_CSR_ADDR           (0xfac00000)#define ECCX_CSR8_OFFSET        (0x8)#define ECCX_CSR11_OFFSET       (0xB)#define ECCX_CSR12_OFFSET       (0xC)#define ECCX_CSR8  (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)#define REG_GPIO_CTRL 0x008/* Definitions for CSR8                                                      */#define ECCX_ENEPSON            0x80    /* Bit 0:					   0= disable and reset SED1386					   1= enable SED1386                 *//* Bit 1:   0= SED1386 in Big Endian mode                                    *//*          1= SED1386 in little endian mode                                 */#define ECCX_LE                 0x40#define ECCX_BE                 0x00/* Bit 2,3: Selection                                                        *//*      00 = Disabled                                                        *//*      01 = CS2 is used for the SED1386                                     *//*      10 = CS5 is used for the SED1386                                     *//*      11 = reserved                                                        */#define ECCX_CS2                0x10#define ECCX_CS5                0x20/* Definitions for CSR12                                                     */#define ECCX_ID                 0x02#define ECCX_860                0x01/* * Memory Periodic Timer Prescaler *//* periodic timer for refresh */#define CFG_MAMR_PTA	58/* * Refresh clock Prescalar */#define CFG_MPTPR	MPTPR_PTP_DIV8/* * MAMR settings for SDRAM *//* 10 column SDRAM */#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)/* * Internal Definitions * * Boot Flags */#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*//*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *//* Configuration variable added by yooth. *//*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *//* * BCSRx * * Board Status and Control Registers * */#define BCSR0 0xFA400000#define BCSR1 0xFA400001#define BCSR2 0xFA400002#define BCSR3 0xFA400003#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */#define BCSR0_LED5		0x04	/* LED5 control 0='on' 1='off' */#define BCSR0_LED4		0x08	/* LED4 control 0='on' 1='off' */#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */#define BCSR0_COLTEST	0x20#define BCSR0_ETHLPBK	0x40#define BCSR0_ETHEN	0x80#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */#define BCSR1_PCVCTL6	0x02#define BCSR1_PCVCTL5	0x04#define BCSR1_PCVCTL4	0x08#define BCSR1_IPB5SEL	0x10#define BCSR2_MIIRST    0x80#define BCSR2_MIIPWRDWN 0x40#define BCSR2_MIICTL    0x08#define BCSR3_BWRTC		0x01	/* Real Time Clock Battery */#define BCSR3_BWNVR		0x02	/* NVRAM Battery */#define BCSR3_RDY_BSY	0x04	/* Flash Operation */#define BCSR3_RPXL		0x08	/* Reserved (reads back '1') */#define BCSR3_D27		0x10	/* Dip Switch settings */#define BCSR3_D26		0x20#define BCSR3_D25		0x40#define BCSR3_D24		0x80/* * Environment setting *//* #define CONFIG_ETHADDR	00:10:EC:00:2C:A2 *//* #define CONFIG_IPADDR	10.10.106.1 *//* #define CONFIG_SERVERIP	10.10.104.11 */#endif	/* __CONFIG_H */