*/#define CFG_INIT_RAM_ADDR       CFG_IMMR#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 * Note also that the logic that sets CFG_RAMBOOT is platform dependent. */#define CFG_MONITOR_BASE        (CFG_FLASH0_BASE + 0x00F00000)#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)#  define CFG_RAMBOOT#endif#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  *//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux *//*----------------------------------------------------------------------- * FLASH and environment organization */#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */#ifndef CFG_RAMBOOT#  define CFG_ENV_IS_IN_FLASH  1#  ifdef CFG_ENV_IN_OWN_SECT#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)#    define CFG_ENV_SECT_SIZE  0x40000#  else#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */#    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */#  endif /* CFG_ENV_IN_OWN_SECT */#else#  define CFG_ENV_IS_IN_NVRAM  1#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)#  define CFG_ENV_SIZE         0x200#endif /* CFG_RAMBOOT *//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */#endif/*----------------------------------------------------------------------- * HIDx - Hardware Implementation-dependent Registers                    2-11 *----------------------------------------------------------------------- * HID0 also contains cache control - initially enable both caches and * invalidate contents, then the final state leaves only the instruction * cache enabled. Note that Power-On and Hard reset invalidate the caches, * but Soft reset does not. * * HID1 has only read-only information - nothing to set. */#define CFG_HID0_INIT   (/*HID0_ICE  |*/\			 /*HID0_DCE  |*/\			 HID0_ICFI |\			 HID0_DCI  |\			 HID0_IFEM |\			 HID0_ABE)#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\			 HID0_IFEM |\			 HID0_ABE  |\			 HID0_EMCP)#define CFG_HID2        0/*----------------------------------------------------------------------- * RMR - Reset Mode Register *----------------------------------------------------------------------- */#define CFG_RMR         0/*----------------------------------------------------------------------- * BCR - Bus Configuration                                       4-25 *----------------------------------------------------------------------- */#define CFG_BCR         (BCR_EBM   |\			 BCR_PLDP  |\			 BCR_EAV   |\			 BCR_NPQM0)/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration                             4-31 *----------------------------------------------------------------------- */#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\			 SIUMCR_APPC10  |\			 SIUMCR_CS10PC01)/*----------------------------------------------------------------------- * SYPCR - System Protection Control                            11-9 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */#define CFG_SYPCR       (SYPCR_SWTC |\			 SYPCR_BMT  |\			 SYPCR_PBME |\			 SYPCR_LBME |\			 SYPCR_SWRI |\			 SYPCR_SWP)/*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control                     4-40 *----------------------------------------------------------------------- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */#define CFG_TMCNTSC     (TMCNTSC_SEC |\			 TMCNTSC_ALR |\			 TMCNTSC_TCF |\			 TMCNTSC_TCE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control                 4-42 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */#define CFG_PISCR       (PISCR_PS  |\			 PISCR_PTF |\			 PISCR_PTE)/*----------------------------------------------------------------------- * SCCR - System Clock Control                                   9-8 *----------------------------------------------------------------------- */#define CFG_SCCR        (SCCR_DFBRG01)/*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration                         13-7 *----------------------------------------------------------------------- */#define CFG_RCCR        0/* * Init Memory Controller: * * Bank Bus     Machine PortSz  Device * ---- ---     ------- ------  ------ *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90) *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) *  3   unused *  4   60x     GPCM     8 bit  Board Regs, LEDs, switches *  5   unused *  6   unused *  7   unused *  8   PCMCIA *  9   unused * 10   unused * 11   unused*//* Bank 0 - FLASH * */#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\			 BRx_PS_64                      |\			 BRx_DECC_NONE                  |\			 BRx_MS_GPCM_P                  |\			 BRx_V)#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\			 ORxG_CSNT                      |\			 ORxG_ACS_DIV1                  |\			 ORxG_SCY_6_CLK                 |\			 ORxG_EHTR)/* Bank 1 - SDRAM * */#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\			 BRx_PS_64                      |\			 BRx_MS_SDRAM_P                 |\			 BRx_V)#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\			 ORxS_BPD_4                     |\			 ORxS_ROWST_PBI0_A8             |\			 ORxS_NUMR_12                   |\			 ORxS_IBID)#define CFG_PSDMR       0x014DA412#define CFG_PSRT	0x79/* Bank 2 - SDRAM * */#define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\			 BRx_PS_32                      |\			 BRx_MS_SDRAM_L                 |\			 BRx_V)#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\			 ORxS_BPD_4                     |\			 ORxS_ROWST_PBI0_A9             |\			 ORxS_NUMR_12)#define CFG_LSDMR       0x0169A512#define CFG_LSRT	0x79#define CFG_MPTPR	(0x0800 & MPTPR_PTP_MSK)/* Bank 4 - On board registers * */#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\			   BRx_PS_8                     |\			   BRx_MS_GPCM_P                |\			   BRx_V)#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\			   ORxG_CSNT                   |\			   ORxG_ACS_DIV1               |\			   ORxG_SCY_5_CLK              |\			   ORxG_TRLX)/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */#define BOOTFLAG_WARM   0x02    /* Software reboot                   */#endif  /* __CONFIG_H */