* interrupt status bit, set PLL multiplication factor ! *//* 0x00B0C0C0 */#define CFG_PLPRCR							\		(	(11 << PLPRCR_MF_SHIFT) |			\			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\		)/*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register		15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */#define SCCR_MASK	SCCR_EBDF11/* 0x01800014 */#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\			 SCCR_DFALCD00)/*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register		11-27 *----------------------------------------------------------------------- *//* 0x00C3 */#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)/*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration Register		19-4 *----------------------------------------------------------------------- *//* TIMEP=2 */#define CFG_RCCR 0x0200/*----------------------------------------------------------------------- * RMDS - RISC Microcode Development Support Control Register *----------------------------------------------------------------------- */#define CFG_RMDS 0/*----------------------------------------------------------------------- * * Interrupt Levels *----------------------------------------------------------------------- */#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*//*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- * */#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )#define CFG_PCMCIA_IO_ADDR	(0xEC000000)#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )/*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- */#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/#define CFG_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/#define CFG_ATA_BASE_ADDR	0xFE100000#define CFG_ATA_IDE0_OFFSET	0x0000#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*//*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */#define CFG_DER	0/* * Init Memory Controller: * * BR0 and OR0 (FLASH) */#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*//* used to re-map FLASH both when starting from SRAM or FLASH: * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses *//* EPROMs are 512kb */#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask *//* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/#define CFG_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \				CFG_OR_TIMING_FLASH)#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \				CFG_OR_TIMING_FLASH)/* 16 bit, bank valid */#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )/* * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000 * * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 */#define ELIC_SACCO_BASE		0xFE000000#define ELIC_SACCO_OR_AM	0xFFFF8000#define ELIC_SACCO_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)#define CFG_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \			ELIC_SACCO_TIMING)#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )/* * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000 * * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 */#define ELIC_EPIC_BASE		0xFE008000#define ELIC_EPIC_OR_AM		0xFFFF8000#define ELIC_EPIC_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \			ELIC_EPIC_TIMING)#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )/* * BR3/OR3: SDRAM * * Multiplexed addresses, GPL5 output to GPL5_A (don't care) */#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )/* * BR4/OR4 - HDLC Address * *  AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 */#define HDLC_ADDR_BASE		0xFE108000	/* HDLC Address area */#define HDLC_ADDR_OR_AM		0xFFFF8000#define HDLC_ADDR_TIMING	OR_SCY_1_CLK#define CFG_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)#define CFG_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )/* * BR5/OR5: SHARC ADSP-2165L * * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 */#define SHARC_BASE		0xFE400000#define SHARC_OR_AM		0xFFC00000#define SHARC_TIMING		OR_SCY_0_CLK#define CFG_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )/* * Memory Periodic Timer Prescaler *//* periodic timer for refresh */#define CFG_MBMR_PTB	204/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*//* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/#if defined (CONFIG_IVML24_16M)# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/#elif defined (CONFIG_IVML24_32M)# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/#elif defined (CONFIG_IVML24_64M)# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/#endif/* * MBMR settings for SDRAM */#if defined (CONFIG_IVML24_16M) /* 8 column SDRAM */# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)#elif defined (CONFIG_IVML24_32M)/* 128 MBit SDRAM */# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)#elif defined (CONFIG_IVML24_64M)/* 128 MBit SDRAM */# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)#endif/* * Internal Definitions * * Boot Flags */#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*/#endif	/* __CONFIG_H */