/*  * A collection of structures, addresses, and values associated with  * the Motorola 860T FADS board.  Copied from the MBX stuff.  * Magnus Damm added defines for 8xxrom and extended bd_info.  * Helmut Buchsbaum added bitvalues for BCSRx  *  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)  *//* * 1999-nov-26: The FADS is using the following physical memorymap: * * ff020000 -> ff02ffff : pcmcia * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom * ff000000 -> ff00ffff : IMAP       internal in the cpu * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom *//* ------------------------------------------------------------------------- *//* * board/config.h - configuration options, board specific */#ifndef __CONFIG_H#define __CONFIG_H/* * High Level Configuration Options * (easy to change) */#include <mpc8xx_irq.h>/* board type */#define CONFIG_FADS		1       /* old/new FADS + new ADS *//* processor type */#define CONFIG_MPC860T		1       /* 860T */#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/#undef	CONFIG_8xx_CONS_SMC2#undef	CONFIG_8xx_CONS_NONE#define CONFIG_BAUDRATE		38400#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/#if 0 /* old FADS */# define CFG_8XX_FACT		12		/* Multiply by 12 */# define CFG_8XX_XIN		4000000		/* 4 MHz in	*/#else /* new FADS */# define CFG_8XX_FACT		10		/* Multiply by 10 */# define CFG_8XX_XIN		5000000		/* 5 MHz in	*/#endif#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))/* should ALWAYS define this, measure_gclk in speed.c is unreliable *//* in general, we always know this for FADS+new ADS anyway */#define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ/* most vanilla kernels do not like this, set to 0 if in doubt */#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */#if 1#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/#else#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/#endif#undef	CONFIG_BOOTARGS#define CONFIG_BOOTCOMMAND			    \    "bootp; "				    \    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	    \    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \    "bootm"#undef	CONFIG_WATCHDOG			/* watchdog disabled		*//* ATA / IDE and partition support */#define CONFIG_MAC_PARTITION    1#define CONFIG_DOS_PARTITION    1#define CONFIG_ISO_PARTITION	1#undef	CONFIG_ATAPI#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*//* choose SCC1 ethernet (10BASET on motherboard) * or FEC ethernet (10/100 on daughterboard) */#if 0#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */#undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */#else   /* all 86x cores have FECs, if in doubt, use it */#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */#define CFG_DISCOVER_PHY#endif#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured#endif/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>/* * Miscellaneous configurable options */#undef	CFG_LONGHELP			/* undef to save memory		*/#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/#else#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/#endif#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define	CFG_MAXARGS	16		/* max number of command args	*/#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/#if (CFG_SDRAM_SIZE)#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/#else#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/#endif#define CFG_LOAD_ADDR	 	0x00100000#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }/* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. *//*---------------------------------------------------------------------- * Internal Memory Mapped Register */#define CFG_IMMR			0xFF000000#define CFG_IMMR_SIZE		((uint)(64 * 1024))/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */#define CFG_INIT_RAM_ADDR	CFG_IMMR#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */#define	CFG_SDRAM_BASE		0x00000000#ifdef CONFIG_FADS# define	CFG_SDRAM_SIZE	0x00400000      /* 4 meg */#else   /* !CONFIG_FADS */ /* old ADS */# define	CFG_SDRAM_SIZE	0x00000000      /* NO SDRAM */#endif#define CFG_FLASH_BASE		0x02800000#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */#define	CFG_MONITOR_LEN		(272 << 10)	/* Reserve 272 kB for Monitor	*/#define CFG_MONITOR_BASE	CFG_FLASH_BASE#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*//*----------------------------------------------------------------------- * FLASH organization */#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/#define	CFG_ENV_IS_IN_FLASH	1#define CFG_ENV_OFFSET		0x00040000#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/#endif/*----------------------------------------------------------------------- * SYPCR - System Protection Control					11-9 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)#else#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)#endif/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration					11-6 *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)/*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control					11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control		11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR	(PISCR_PS | PISCR_PITF)