/* * (C) Copyright 2001-2003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * board/config.h - configuration options, board specific */#ifndef __CONFIG_H#define __CONFIG_H/* * High Level Configuration Options * (easy to change) */#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/#define CONFIG_4xx		1	/* ...member of PPC4xx family   */#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/#define CONFIG_CPCI405_VER2     1       /* ...version 2                 */#define CONFIG_CPCI405AB        1       /* ...and special AB version    */#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */#define CONFIG_BAUDRATE		9600#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/#if 0#define CONFIG_PREBOOT                                                          \	"crc32 f0207004 ffc 0;"                                                 \	"if cmp 0 f0207000 1;"                                                  \	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \	"else;echo Old CRC is bad;fi"#endif#undef	CONFIG_BOOTARGS#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* default boot command	*/#undef  CONFIG_LOADS_ECHO		/* echo on for serial download	*/#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/#define CONFIG_MII		1	/* MII PHY management		*/#define	CONFIG_PHY_ADDR		0	/* PHY address			*/#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \				 CONFIG_BOOTP_DNS | \				 CONFIG_BOOTP_DNS2 | \				 CONFIG_BOOTP_SEND_HOSTNAME )#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \				CFG_CMD_DHCP	| \				CFG_CMD_PCI	| \				CFG_CMD_IRQ	| \				CFG_CMD_IDE	| \				CFG_CMD_ELF	| \				CFG_CMD_DATE	| \				CFG_CMD_JFFS2	| \				CFG_CMD_I2C	| \				CFG_CMD_MII	| \				CFG_CMD_PING	| \				CFG_CMD_EEPROM  )#define CONFIG_MAC_PARTITION#define CONFIG_DOS_PARTITION/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*//* * Miscellaneous configurable options */#define CFG_LONGHELP			/* undef to save memory		*/#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/#ifdef	CFG_HUSH_PARSER#define	CFG_PROMPT_HUSH_PS2	"> "#endif#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/#else#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/#endif#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS	16		/* max number of command args	*/#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */#define CFG_BASE_BAUD       691200/* The following table includes the supported baudrates */#define CFG_BAUDRATE_TABLE      \	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \	 57600, 115200, 230400, 460800, 921600 }#define CFG_LOAD_ADDR	0x100000	/* default load address */#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac *//*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */#define PCI_HOST_FORCE  1               /* configure as pci host        */#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */#define CONFIG_PCI			/* include pci support	        */#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */#define CONFIG_PCI_PNP			/* do pci plug-and-play         */					/* resource configuration       */#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   *//*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- */#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */#undef  CONFIG_IDE_LED                  /* no led for ide supported     */#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */#define	CFG_ATA_BASE_ADDR	0xF0100000#define	CFG_ATA_IDE0_OFFSET	0x0000#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/