/* * (C) Copyright 2000 * Murray Jensen <Murray.Jensen@cmst.csiro.au> * * (C) Copyright 2000 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * * (C) Copyright 2001 * Advent Networks, Inc. <http://www.adventnetworks.com> * Jay Monkman <jtm@smoothsmoothie.com> * * Configuration settings for the WindRiver SBC8260 board. *	See http://www.windriver.com/products/html/sbc8260.html * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __CONFIG_H#define __CONFIG_H#undef DEBUG		      /* General debug */#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */#undef CONFIG_LOGBUFFER       /* External logbuffer support *//***************************************************************************** * * These settings must match the way _your_ board is set up * *****************************************************************************//* What is the oscillator's (UX2) frequency in Hz? */#define CONFIG_8260_CLKIN  66666600/*----------------------------------------------------------------------- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual *----------------------------------------------------------------------- * What should MODCK_H be? It is dependent on the oscillator * frequency, MODCK[1-3], and desired CPM and core frequencies. * Here are some example values (all frequencies are in MHz): * * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8 * -------   ----------	 ---	---    ----  -----  -----  ----- * 0x1	     0x5	 33	100    133   Open   Close  Open * 0x1	     0x6	 33	100    166   Open   Open   Close * 0x1	     0x7	 33	100    200   Open   Open   Open * * 0x2	     0x2	 33	133    133   Close  Open   Close * 0x2	     0x3	 33	133    166   Close  Open   Open * 0x2	     0x4	 33	133    200   Open   Close  Close * 0x2	     0x5	 33	133    233   Open   Close  Open * 0x2	     0x6	 33	133    266   Open   Open   Close * * 0x5	     0x5	 66	133    133   Open   Close  Open * 0x5	     0x6	 66	133    166   Open   Open   Close * 0x5	     0x7	 66	133    200   Open   Open   Open * 0x6	     0x0	 66	133    233   Close  Close  Close * 0x6	     0x1	 66	133    266   Close  Close  Open * 0x6	     0x2	 66	133    300   Close  Open   Close */#define CFG_SBC_MODCK_H 0x05/* Define this if you want to boot from 0x00000100. If you don't define * this, you will need to program the bootloader to 0xfff00000, and * get the hardware reset config words at 0xfe000000. The simplest * way to do that is to program the bootloader at both addresses. * It is suggested that you just let U-Boot live at 0x00000000. */#define CFG_SBC_BOOT_LOW 1/* What should the base address of the main FLASH be and how big is * it (in MBytes)?  This must contain TEXT_BASE from board/sacsng/config.mk * The main FLASH is whichever is connected to *CS0. */#define CFG_FLASH0_BASE 0x40000000#define CFG_FLASH0_SIZE 2/* What should the base address of the secondary FLASH be and how big * is it (in Mbytes)?  The secondary FLASH is whichever is connected * to *CS6. */#define CFG_FLASH1_BASE 0x60000000#define CFG_FLASH1_SIZE 2/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes */#define CONFIG_VERY_BIG_RAM	1/* What should be the base address of SDRAM DIMM and how big is * it (in Mbytes)?  This will normally auto-configure via the SPD.*/#define CFG_SDRAM0_BASE 0x00000000#define CFG_SDRAM0_SIZE 64/* * Memory map example with 64 MB DIMM: * *     0x0000 0000     Exception Vector code, 8k *	     : *     0x0000 1FFF *     0x0000 2000     Free for Application Use *	     : *	     : * *	     : *	     : *     0x03F5 FF30     Monitor Stack (Growing downward) *		       Monitor Stack Buffer (0x80) *     0x03F5 FFB0     Board Info Data *     0x03F6 0000     Malloc Arena *	     :		    CFG_ENV_SECT_SIZE, 16k *	     :		    CFG_MALLOC_LEN,    128k *     0x03FC 0000     RAM Copy of Monitor Code *	     :		    CFG_MONITOR_LEN,   256k *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1 */#define CONFIG_POST		(CFG_POST_MEMORY | \				 CFG_POST_CPU)/* * select serial console configuration * * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 * for SCC). * * if CONFIG_CONS_NONE is defined, then the serial console routines must * defined elsewhere. */#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */#undef	CONFIG_CONS_NONE		/* define if console on neither */#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console *//* * select ethernet configuration * * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be * defined elsewhere (as for the console), or CFG_CMD_NET must be removed * from CONFIG_COMMANDS to remove support for networking. */#undef	CONFIG_ETHER_ON_SCC#define CONFIG_ETHER_ON_FCC#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */#ifdef	CONFIG_ETHER_ON_SCC#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */#endif	/* CONFIG_ETHER_ON_SCC */#ifdef	CONFIG_ETHER_ON_FCC#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */#define CONFIG_MII			/* MII PHY management		*/#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*//* * Port pins used for bit-banged MII communictions (if applicable). */#define MDIO_PORT	2	        /* Port A=0, B=1, C=2, D=3 */#define MDIO_ACTIVE	(iop->pdir |=  0x40000000)#define MDIO_TRISTATE	(iop->pdir &= ~0x40000000)#define MDIO_READ	((iop->pdat &  0x40000000) != 0)#define MDIO(bit)	if(bit) iop->pdat |=  0x40000000; \			else	iop->pdat &= ~0x40000000#define MDC(bit)	if(bit) iop->pdat |=  0x80000000; \			else	iop->pdat &= ~0x80000000#define MIIDELAY	udelay(50)#endif	/* CONFIG_ETHER_ON_FCC */#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)/* *  - RX clk is CLK11 *  - TX clk is CLK12 */# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)/* * - Rx-CLK is CLK13 * - Tx-CLK is CLK14 * - Select bus for bd/buffers (see 28-13) * - Enable Full Duplex in FSMR */# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)# define CFG_CPMFCR_RAMTYPE	0# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */#define CONFIG_SHOW_BOOT_PROGRESS 1	/* boot progress enabled	*//* * Configure for RAM tests. */#undef  CFG_DRAM_TEST			/* calls other tests in board.c	*//* * Status LED for power up status feedback. */#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/#define STATUS_LED_PAR		im_ioport.iop_ppara#define STATUS_LED_DIR		im_ioport.iop_pdira#define STATUS_LED_ODR		im_ioport.iop_podra#define STATUS_LED_DAT		im_ioport.iop_pdata#define STATUS_LED_BIT		0x00000800	/* LED 0 is on PA.20	*/#define STATUS_LED_PERIOD	(CFG_HZ)#define STATUS_LED_STATE	STATUS_LED_OFF#define STATUS_LED_BIT1		0x00001000	/* LED 1 is on PA.19	*/#define STATUS_LED_PERIOD1	(CFG_HZ)#define STATUS_LED_STATE1	STATUS_LED_OFF#define STATUS_LED_BIT2		0x00002000	/* LED 2 is on PA.18	*/#define STATUS_LED_PERIOD2	(CFG_HZ/2)#define STATUS_LED_STATE2	STATUS_LED_ON#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/#define STATUS_LED_YELLOW	0#define STATUS_LED_GREEN	1#define STATUS_LED_RED		2#define STATUS_LED_BOOT		1/* * Select SPI support configuration */#define CONFIG_SOFT_SPI		/* Enable SPI driver */#define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */#undef  DEBUG_SPI               /* Disable SPI debugging *//* * Software (bit-bang) SPI driver configuration */#ifdef CONFIG_SOFT_SPI/* * Software (bit-bang) SPI driver configuration */#define I2C_SCLK	0x00002000      /* PD 18: Shift clock */#define I2C_MOSI	0x00004000      /* PD 17: Master Out, Slave In */#define I2C_MISO	0x00008000      /* PD 16: Master In, Slave Out */#undef  SPI_INIT			/* no port initialization needed */#define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)#define SPI_SDA(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI#define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK#define SPI_DELAY                       /* No delay is needed */#endif /* CONFIG_SOFT_SPI *//* * select I2C support configuration * * Supported configurations are {none, software, hardware} drivers. * If the software driver is chosen, there are some additional * configuration items that the driver uses to drive the port pins. */#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/#define CFG_I2C_SLAVE		0x7F/* * Software (bit-bang) I2C driver configuration */#ifdef CONFIG_SOFT_I2C#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */#define I2C_ACTIVE	(iop->pdir |=  0x00010000)#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)#define I2C_READ	((iop->pdat & 0x00010000) != 0)#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \			else    iop->pdat &= ~0x00010000#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \			else    iop->pdat &= ~0x00020000#define I2C_DELAY	udelay(20)	/* 1/4 I2C clock duration */#endif /* CONFIG_SOFT_I2C *//* Define this to reserve an entire FLASH sector for * environment variables. Otherwise, the environment will be * put in the same sector as U-Boot, and changing variables * will erase U-Boot temporarily */#define CFG_ENV_IN_OWN_SECT	1/* Define this to contain any number of null terminated strings that * will be part of the default enviroment compiled into the boot image. */#define CONFIG_EXTRA_ENV_SETTINGS \"quiet=0\0" \"serverip=192.168.123.205\0" \"ipaddr=192.168.123.203\0" \"checkhostname=VR8500\0" \"reprog="\    "bootp; " \    "tftpboot 0x140000 /bdi2000/u-boot.bin; " \    "protect off 60000000 6003FFFF; " \    "erase 60000000 6003FFFF; " \    "cp.b 140000 60000000 $(filesize); " \    "protect on 60000000 6003FFFF\0" \"copyenv="\    "protect off 60040000 6004FFFF; " \    "erase 60040000 6004FFFF; " \    "cp.b 40040000 60040000 10000; " \    "protect on 60040000 6004FFFF\0" \"copyprog="\    "protect off 60000000 6003FFFF; " \    "erase 60000000 6003FFFF; " \    "cp.b 40000000 60000000 40000; " \    "protect on 60000000 6003FFFF\0" \"zapenv="\    "protect off 40040000 4004FFFF; " \    "erase 40040000 4004FFFF; " \    "protect on 40040000 4004FFFF\0" \"zapotherenv="\    "protect off 60040000 6004FFFF; " \    "erase 60040000 6004FFFF; " \    "protect on 60040000 6004FFFF\0" \"root-on-initrd="\    "setenv bootcmd "\    "version\\;" \    "echo\\;" \    "bootp\\;" \    "setenv bootargs root=/dev/ram0 rw quiet " \    "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \