/* * (C) Copyright 2000 * Murray Jensen <Murray.Jensen@cmst.csiro.au> * * (C) Copyright 2000 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * * (C) Copyright 2001 * Advent Networks, Inc. <http://www.adventnetworks.com> * Jay Monkman <jtm@smoothsmoothie.com> * * Configuation settings for the WindRiver PPMC8260 board. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __CONFIG_H#define __CONFIG_H/***************************************************************************** * * These settings must match the way _your_ board is set up * *****************************************************************************//* What is the oscillator's (UX2) frequency in Hz? */#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)/*----------------------------------------------------------------------- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual *----------------------------------------------------------------------- * What should MODCK_H be? It is dependent on the oscillator * frequency, MODCK[1-3], and desired CPM and core frequencies. * Here are some example values (all frequencies are in MHz): * * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8 * -------   ----------	 ---	---    ----  -----  -----  ----- * 0x2	     0x2	 33	133    133   Close  Open   Close * 0x2	     0x3	 33	133    166   Close  Open   Open * 0x2	     0x4	 33	133    200   Open   Close  Close * 0x2	     0x5	 33	133    233   Open   Close  Open * 0x2	     0x6	 33	133    266   Open   Open   Close * * 0x5	     0x5	 66	133    133   Open   Close  Open * 0x5	     0x6	 66	133    166   Open   Open   Close * 0x5	     0x7	 66	133    200   Open   Open   Open * 0x6	     0x0	 66	133    233   Close  Close  Close * 0x6	     0x1	 66	133    266   Close  Close  Open * 0x6	     0x2	 66	133    300   Close  Open   Close */#define CFG_PPMC_MODCK_H 0x05/* Define this if you want to boot from 0x00000100. If you don't define * this, you will need to program the bootloader to 0xfff00000, and * get the hardware reset config words at 0xfe000000. The simplest * way to do that is to program the bootloader at both addresses. * It is suggested that you just let U-Boot live at 0x00000000. */#define CFG_PPMC_BOOT_LOW 1/* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk * The main FLASH is whichever is connected to *CS0. U-Boot expects * this to be the SIMM. */#define CFG_FLASH0_BASE 0xFE000000#define CFG_FLASH0_SIZE 16/* What should be the base address of the first SDRAM DIMM and how big is * it (in Mbytes)?*/#define CFG_SDRAM0_BASE 0x00000000#define CFG_SDRAM0_SIZE 128/* What should be the base address of the second SDRAM DIMM and how big is * it (in Mbytes)?*/#define CFG_SDRAM1_BASE 0x08000000#define CFG_SDRAM1_SIZE 128/* What should be the base address of the on board SDRAM and how big is * it (in Mbytes)?*/#define CFG_SDRAM2_BASE 0x38000000#define CFG_SDRAM2_SIZE 16/* What should be the base address of the MAILBOX  and how big is it * (in Bytes) * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000 */#define CFG_MAILBOX_BASE 0x32000000#define CFG_MAILBOX_SIZE 8192/* What is the base address of the I/O select lines and how big is it * (In Mbytes)? */#define CFG_IOSELECT_BASE 0xE0000000#define CFG_IOSELECT_SIZE 32/* What should be the base address of the LEDs and switch S0? * If you don't want them enabled, don't define this. */#define CFG_LED_BASE 0xF1000000/* * PPMC8260 with 256 16 MB DIMM: * *     0x0000 0000     Exception Vector code, 8k *	     : *     0x0000 1FFF *     0x0000 2000     Free for Application Use *	     : *	     : * *	     : *	     : *     0x0FF5 FF30     Monitor Stack (Growing downward) *		       Monitor Stack Buffer (0x80) *     0x0FF5 FFB0     Board Info Data *     0x0FF6 0000     Malloc Arena *	     :		    CFG_ENV_SECT_SIZE, 256k *	     :		    CFG_MALLOC_LEN,    128k *     0x0FFC 0000     RAM Copy of Monitor Code *	     :		    CFG_MONITOR_LEN,   256k *     0x0FFF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1 *//* * select serial console configuration * * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 * for SCC). * * if CONFIG_CONS_NONE is defined, then the serial console routines must * defined elsewhere. * The console can be on SMC1 or SMC2 */#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */#undef	CONFIG_CONS_NONE		/* define if console on neither */#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console *//* * select ethernet configuration * * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be * defined elsewhere (as for the console), or CFG_CMD_NET must be removed * from CONFIG_COMMANDS to remove support for networking. */#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/#define CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */#define CONFIG_MII			/* MII PHY management	*/#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*//* * Port pins used for bit-banged MII communictions (if applicable). */#define MDIO_PORT	2	/* Port C */#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)#define MDIO_READ	((iop->pdat &  0x00400000) != 0)#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \			else	iop->pdat &= ~0x00400000#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \			else	iop->pdat &= ~0x00200000#define MIIDELAY	udelay(1)/* Define this to reserve an entire FLASH sector (256 KB) for * environment variables. Otherwise, the environment will be * put in the same sector as U-Boot, and changing variables * will erase U-Boot temporarily */#define CFG_ENV_IN_OWN_SECT	1/* Define to allow the user to overwrite serial and ethaddr */#define CONFIG_ENV_OVERWRITE/* What should the console's baud rate be? */#define CONFIG_BAUDRATE		9600/* Ethernet MAC address */#define CONFIG_ETHADDR		00:a0:1e:90:2b:00/* Define this to set the last octet of the ethernet address * from the DS0-DS7 switch and light the leds with the result * The DS0-DS7 switch and the leds are backwards with respect * to each other. DS7 is on the board edge side of both the * led strip and the DS0-DS7 switch. */#define CONFIG_MISC_INIT_R/* Set to a positive value to delay for running BOOTCOMMAND */#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */#if 0/* Be selective on what keys can delay or stop the autoboot process *     To stop	use: " " */# define CONFIG_AUTOBOOT_KEYED# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"# define CONFIG_AUTOBOOT_STOP_STR	" "# undef CONFIG_AUTOBOOT_DELAY_STR# define DEBUG_BOOTKEYS		0#endif/* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */#define CONFIG_BOOT_ROOT_INITRD 0	/* Use ram disk for the root file system */#define CONFIG_BOOT_ROOT_NFS	1	/* Use a NFS mounted root file system */#if CONFIG_BOOT_ROOT_INITRD#define CONFIG_BOOTCOMMAND \	"version;" \	"echo;" \	"bootp;" \	"setenv bootargs root=/dev/ram0 rw " \	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \	"bootm"#endif /* CONFIG_BOOT_ROOT_INITRD */#if CONFIG_BOOT_ROOT_NFS#define CONFIG_BOOTCOMMAND \	"version;" \	"echo;" \	"bootp;" \	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \	"bootm"#endif /* CONFIG_BOOT_ROOT_NFS *//* Add support for a few extra bootp options like: *	- File size *	- DNS */#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \				 CONFIG_BOOTP_BOOTFILESIZE | \				 CONFIG_BOOTP_DNS)/* undef this to save memory */#define CFG_LONGHELP/* Monitor Command Prompt */#define CFG_PROMPT		"=> "/* What U-Boot subsytems do you want enabled? */#define CONFIG_COMMANDS		(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \				CFG_CMD_ELF	| \				CFG_CMD_ASKENV	| \				CFG_CMD_ECHO	| \				CFG_CMD_REGINFO | \				CFG_CMD_MEMTEST | \				CFG_CMD_MII	| \				CFG_CMD_IMMAP)/* Where do the internal registers live? */#define CFG_IMMR		0xf0000000/***************************************************************************** * * You should not have to modify any of the following settings * *****************************************************************************/#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */#define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  *//* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>/* * Miscellaneous configurable options */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */#else#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */#endif/* Print Buffer Size */#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)#define CFG_MAXARGS		32	/* max number of command args	*/#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */#define CFG_LOAD_ADDR		0x140000   /* default load address */#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */					/* the exception vector table */					/* to the end of the DRAM  */					/* less monitor and malloc area */#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \				+ CFG_MALLOC_LEN \				+ CFG_ENV_SECT_SIZE \				+ CFG_STACK_USAGE )#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \				- CFG_MEM_END_USAGE )