/* * (C) Copyright 2001-2003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * board/config.h - configuration options, board specific */#ifndef __CONFIG_H#define __CONFIG_H/* * High Level Configuration Options * (easy to change) */#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/#define CONFIG_4xx		1	/* ...member of PPC4xx family   */#define CONFIG_HUB405		1	/* ...on a ASH405 board 	*/#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */#define CONFIG_BAUDRATE		9600#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/#undef	CONFIG_BOOTARGS#define CONFIG_RAMBOOTCOMMAND							\	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\	"bootm ffc00000 ffca0000"#define CONFIG_NFSBOOTCOMMAND							\	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\	"bootm ffc00000"#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/#define CONFIG_MII		1	/* MII PHY management		*/#define	CONFIG_PHY_ADDR		0	/* PHY address			*/#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \				CFG_CMD_DHCP	| \				CFG_CMD_IRQ	| \				CFG_CMD_ELF	| \				CFG_CMD_NAND	| \				CFG_CMD_I2C	| \				CFG_CMD_MII	| \				CFG_CMD_PING	| \				CFG_CMD_EEPROM  )/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*//* * Miscellaneous configurable options */#define CFG_LONGHELP			/* undef to save memory		*/#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/#ifdef	CFG_HUSH_PARSER#define	CFG_PROMPT_HUSH_PS2	"> "#endif#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/#else#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/#endif#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS	16		/* max number of command args	*/#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */#define CFG_BASE_BAUD       691200#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  *//* The following table includes the supported baudrates */#define CFG_BAUDRATE_TABLE      \	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \	 57600, 115200, 230400, 460800, 921600 }#define CFG_LOAD_ADDR	0x100000	/* default load address */#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac *//*----------------------------------------------------------------------- * NAND-FLASH stuff *----------------------------------------------------------------------- */#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/#define SECTORSIZE 512#define ADDR_COLUMN 1#define ADDR_PAGE 2#define ADDR_COLUMN_PAGE 3#define NAND_ChipID_UNKNOWN 	0x00#define NAND_MAX_FLOORS 1#define NAND_MAX_CHIPS 1#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))/*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */#define PCI_HOST_FORCE  1               /* configure as pci host        */#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */#undef  CONFIG_PCI			/* include pci support	        */#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */#undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */					/* resource configuration       */#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   *//*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */