/* * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Keith Outwater, keith_outwater@mvis.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * board/config_GEN860T.h - board specific configuration options */#ifndef __CONFIG_GEN860T_H#define __CONFIG_H/* * High Level Configuration Options */#define CONFIG_MPC860#define CONFIG_GEN860T/* * Identify the board */#if !defined(CONFIG_SC)#define CONFIG_IDENT_STRING				" B2"#else#define CONFIG_IDENT_STRING				" SC"#endif/* * Don't depend on the RTC clock to determine clock frequency - * the 860's internal rtc uses a 32.768 KHz clock which is * generated by the DS1337 - and the DS1337 clock can be turned off. */#if !defined(CONFIG_SC)#define	CONFIG_8xx_GCLK_FREQ			66600000#else#define	CONFIG_8xx_GCLK_FREQ			48000000#endif/* * The RS-232 console port is on SMC1 */#define	CONFIG_8xx_CONS_SMC1#define CONFIG_BAUDRATE					38400/* * Set allowable console baud rates */#define CFG_BAUDRATE_TABLE				{ 9600,		\							 		 	  19200,	\							 		 	  38400,	\									 	  57600,	\									 	  115200,	\										}/* * Print console information */#undef	 CFG_CONSOLE_INFO_QUIET/* * Set the autoboot delay in seconds.  A delay of -1 disables autoboot */#define CONFIG_BOOTDELAY				5/* * Pass the clock frequency to the Linux kernel in units of MHz */#define	CONFIG_CLOCKS_IN_MHZ#define CONFIG_PREBOOT		\	"echo;echo"#undef	CONFIG_BOOTARGS#define CONFIG_BOOTCOMMAND	\	"bootp;" \	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \	"bootm"/* * Turn off echo for serial download by default.  Allow baud rate to be changed * for downloads */#undef	CONFIG_LOADS_ECHO#define	CFG_LOADS_BAUD_CHANGE/* * Set default load address for tftp network downloads */#define	CFG_TFTP_LOADADDR				0x01000000/* * Turn off the watchdog timer */#undef	CONFIG_WATCHDOG/* * Do not reboot if a panic occurs */#define CONFIG_PANIC_HANG/* * Enable the status LED */#define	CONFIG_STATUS_LED/* * Reset address. We pick an address such that when an instruction * is executed at that address, a machine check exception occurs */#define CFG_RESET_ADDRESS				((ulong) -1)/* * BOOTP options */#define CONFIG_BOOTP_MASK				( CONFIG_BOOTP_DEFAULT		| \									  	  CONFIG_BOOTP_BOOTFILESIZE   \										)/* * The GEN860T network interface uses the on-chip 10/100 FEC with * an Intel LXT971A PHY connected to the 860T's MII. The PHY's * MII address is hardwired on the board to zero. */#define CONFIG_FEC_ENET#define CFG_DISCOVER_PHY#define CONFIG_MII#define CONFIG_PHY_ADDR         		0/* * Set default IP stuff just to get bootstrap entries into the * environment so that we can autoscript the full default environment. */#define CONFIG_ETHADDR					9a:52:63:15:85:25#define CONFIG_SERVERIP					10.0.4.201#define CONFIG_IPADDR					10.0.4.111/* * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to * the MPC860T I2C interface. */#define CFG_I2C_EEPROM_ADDR				0x50#define CFG_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/#define	CFG_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/#define CFG_ENV_EEPROM_SIZE				(32 * 1024)/* * Enable I2C and select the hardware/software driver */#define CONFIG_HARD_I2C		1				/* CPM based I2C			*/#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/#ifdef CONFIG_HARD_I2C#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/#endif#ifdef CONFIG_SOFT_I2C#define PB_SCL				0x00000020		/* PB 26					*/#define PB_SDA				0x00000010		/* PB 27 					*/#define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)#define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)#define I2C_READ			((immr->im_cpm.cp_pbdat & PB_SDA) != 0)#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \								else    immr->im_cpm.cp_pbdat &= ~PB_SDA#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \								else    immr->im_cpm.cp_pbdat &= ~PB_SCL#define I2C_DELAY			udelay(5)		/* 1/4 I2C clock duration	*/#endif/* * Allow environment overwrites by anyone */#define CONFIG_ENV_OVERWRITE#if !defined(CONFIG_SC)/* * The MPC860's internal RTC is horribly broken in rev D masks. Three * internal MPC860T circuit nodes were inadvertently left floating; this * causes KAPWR current in power down mode to be three orders of magnitude * higher than specified in the datasheet (from 10 uA to 10 mA).  No * reasonable battery can keep that kind RTC running during powerdown for any * length of time, so we use an external RTC on the I2C bus instead. */#define CONFIG_RTC_DS1337#define CFG_I2C_RTC_ADDR				0x68#else/* * No external RTC on SC variant, so we're stuck with the internal one. */#define	CONFIG_RTC_MPC8xx#endif/* * Power On Self Test support */#define CONFIG_POST			  ( CFG_POST_CACHE		| \								CFG_POST_MEMORY		| \								CFG_POST_CPU		| \								CFG_POST_UART		| \								CFG_POST_SPR )#ifdef CONFIG_POST#define CFG_CMD_POST_DIAG CFG_CMD_DIAG#else#define CFG_CMD_POST_DIAG		0#endif/* * List of available monitor commands.  Use the system default list * plus add some of the "non-standard" commands back in. * See ./cmd_confdefs.h */#define BASE_CONFIG_COMMANDS	( CONFIG_CMD_DFL	| \								CFG_CMD_ASKENV	| \								CFG_CMD_DHCP	| \								CFG_CMD_I2C		| \								CFG_CMD_EEPROM	| \								CFG_CMD_REGINFO	| \								CFG_CMD_IMMAP	| \								CFG_CMD_ELF		| \								CFG_CMD_DATE	| \								CFG_CMD_FPGA	| \								CFG_CMD_MII 	| \								CFG_CMD_BEDBUG	| \								CFG_CMD_POST_DIAG )#if !defined(CONFIG_SC)#define	CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )#else#define CONFIG_COMMANDS	BASE_CONFIG_COMMANDS#endif/* * There is no IDE/PCMCIA hardware support on the board. */#undef  CONFIG_IDE_PCMCIA#undef  CONFIG_IDE_LED#undef  CONFIG_IDE_RESET/* * Enable the call to misc_init_r() for miscellaneous platform * dependent initialization. */#define CONFIG_MISC_INIT_R/* * Enable call to last_stage_init() so we can twiddle some LEDS :) */#define CONFIG_LAST_STAGE_INIT/* * Virtex2 FPGA configuration support */#define CONFIG_FPGA_COUNT		1#define CONFIG_FPGA				CFG_XILINX_VIRTEX2#define CFG_FPGA_PROG_FEEDBACK/************************************************************************ * This must be included AFTER the definition of any CONFIG_COMMANDS */#include <cmd_confdefs.h>/* * Verbose help from command monitor. */#define	CFG_LONGHELP#if !defined(CONFIG_SC)#define	CFG_PROMPT			"B2> "#else#define	CFG_PROMPT			"SC> "#endif/* * Use the "hush" command parser */#define	CFG_HUSH_PARSER#define	CFG_PROMPT_HUSH_PS2	"> "/* * Set buffer size for console I/O */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define	CFG_CBSIZE			1024#else#define	CFG_CBSIZE			256#endif/* * Print buffer size */#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* * Maximum number of arguments that a command can accept */#define	CFG_MAXARGS			16/* * Boot argument buffer size */#define CFG_BARGSIZE		CFG_CBSIZE/* * Default memory test range */#define CFG_MEMTEST_START	0x0100000#define CFG_MEMTEST_END		(CFG_MEMTEST_START  + (128 * 1024))/* * Select the more full-featured memory test */#define	CFG_ALT_MEMTEST/* * Default load address */#define	CFG_LOAD_ADDR		0x01000000/* * Set decrementer frequency (1 ms ticks) */#define	CFG_HZ				1000/* * Device memory map (after SDRAM remap to 0x0): * * CS		Device				Base Addr	Size * ---------------------------------------------------- * CS0*		Flash				0x40000000	64 M * CS1*		SDRAM				0x00000000	16 M * CS2*		Disk-On-Chip		0x50000000	32 K * CS3*		FPGA				0x60000000	64 M * CS4*		SelectMap			0x70000000	32 K * CS5*		Mil-Std 1553 I/F	0x80000000	32 K * CS6*		Unused * CS7*		Unused * IMMR		860T Registers		0xfff00000 *//* * Base addresses and block sizes */#define CFG_IMMR			0xFF000000#define SDRAM_BASE			0x00000000#define SDRAM_SIZE			(64 * 1024 * 1024)#define FLASH_BASE			0x40000000#define FLASH_SIZE			(16 * 1024 * 1024)#define DOC_BASE			0x50000000#define DOC_SIZE			(32 * 1024)#define FPGA_BASE			0x60000000#define FPGA_SIZE			(64 * 1024 * 1024)#define SELECTMAP_BASE		0x70000000#define SELECTMAP_SIZE		(32 * 1024)