#define M1553_BASE			0x80000000#define M1553_SIZE			(64 * 1024)/* * Definitions for initial stack pointer and data area (in DPRAM) */#define CFG_INIT_RAM_ADDR		CFG_IMMR#define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/#define	CFG_INIT_DATA_SIZE		64  	/* # bytes reserved for initial data*/#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)#define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET/* * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */#define	CFG_SDRAM_BASE			SDRAM_BASE/* * FLASH organization */#define CFG_FLASH_BASE			FLASH_BASE#define CFG_FLASH_SIZE			FLASH_SIZE#define CFG_FLASH_SECT_SIZE		(128 * 1024)#define CFG_MAX_FLASH_BANKS		1#define CFG_MAX_FLASH_SECT		128/* * The timeout values are for an entire chip and are in milliseconds. * Yes I know that the write timeout is huge.  Accroding to the * datasheet a single byte takes 630 uS (round to 1 ms) max at worst * case VCC and temp after 100K programming cycles.  It works out * to 280 minutes (might as well be forever). */#define CFG_FLASH_ERASE_TOUT	(CFG_MAX_FLASH_SECT * 5000)#define CFG_FLASH_WRITE_TOUT	(CFG_MAX_FLASH_SECT * 128 * 1024 * 1)/* * Allow direct writes to FLASH from tftp transfers (** dangerous **) */#define	CFG_DIRECT_FLASH_TFTP/* * Reserve memory for U-Boot. */#define CFG_MAX_UBOOT_SECTS		4#define	CFG_MONITOR_LEN			(CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)#define CFG_MONITOR_BASE		CFG_FLASH_BASE/* * Select environment placement.  NOTE that u-boot.lds must * be edited if this is changed! */#undef	CFG_ENV_IS_IN_FLASH#define CFG_ENV_IS_IN_EEPROM#if defined(CFG_ENV_IS_IN_EEPROM)#define CFG_ENV_SIZE			(2 * 1024)#define CFG_ENV_OFFSET			(CFG_ENV_EEPROM_SIZE - (8 * 1024))#else#define CFG_ENV_SIZE			0x1000#define CFG_ENV_SECT_SIZE		CFG_FLASH_SECT_SIZE/* * This ultimately gets passed right into the linker script, so we have to * use a number :( */#define CFG_ENV_OFFSET			0x060000#endif/* * Reserve memory for malloc() */#define	CFG_MALLOC_LEN		(128 * 1024)/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define	CFG_BOOTMAPSZ		(8 * 1024 * 1024)/* * Cache Configuration */#define CFG_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CFG_CACHELINE_SHIFT		4	/* log base 2 of above value		*/#endif/*------------------------------------------------------------------------ * SYPCR - System Protection Control							UM 11-9 * ----------------------------------------------------------------------- * SYPCR can only be written once after reset! * * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR	( SYPCR_SWTC	| \					  SYPCR_BMT 	| \					  SYPCR_BME 	| \					  SYPCR_SWF 	| \					  SYPCR_SWE 	| \					  SYPCR_SWRI	| \					  SYPCR_SWP		  \					)#else#define CFG_SYPCR	( SYPCR_SWTC	| \					  SYPCR_BMT 	| \					  SYPCR_BME 	| \					  SYPCR_SWF 	| \					  SYPCR_SWP		  \					)#endif/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration							UM 11-6 *----------------------------------------------------------------------- * Set debug pin mux, enable SPKROUT and GPLB5*. */#define CFG_SIUMCR	( SIUMCR_DBGC11 | \					  SIUMCR_DBPC11 | \					  SIUMCR_MLRC11	| \					  SIUMCR_GB5E	  \					)/*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control							UM 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freeze enabled */#define CFG_TBSCR	( TBSCR_REFA | \					  TBSCR_REFB | \					  TBSCR_TBF	   \					)/*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register			UM 11-27 *----------------------------------------------------------------------- */#define CFG_RTCSC	( RTCSC_SEC	| \					  RTCSC_ALR | \					  RTCSC_RTF | \					  RTCSC_RTE	  \					)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control				UM 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR	( PISCR_PS		| \					  PISCR_PITF	  \					)/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register			UM 15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit. Set MF for 1:2:1 mode. */#define CFG_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \					  PLPRCR_SPLSS	| \					  PLPRCR_TEXPS	| \					  PLPRCR_TMIST	  \					)/*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register				UM 15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */#define SCCR_MASK   SCCR_EBDF11#if !defined(CONFIG_SC)#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \					  SCCR_DFNL000		| \					  SCCR_DFNH000		  \					)#else#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \					  SCCR_DFNL000		| \					  SCCR_DFNH000		| \					  SCCR_RTDIV		| \					  SCCR_RTSEL		  \					)#endif/*----------------------------------------------------------------------- * DER - Debug Enable Register									UM 37-46 *----------------------------------------------------------------------- * Mask all events that can cause entry into debug mode */#define CFG_DER				0/* * Initialize Memory Controller: * * BR0 and OR0 (FLASH memory) */#define FLASH_BASE0_PRELIM	FLASH_BASE/* * Flash address mask */#define CFG_PRELIM_OR_AM	0xfe000000/* * FLASH timing: * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM	| \							  OR_ACS_DIV2	| \							  OR_BI			| \							  OR_SCY_2_CLK	| \							  OR_TRLX		| \							  OR_EHTR		  \							)#define CFG_OR0_PRELIM	( CFG_PRELIM_OR_AM		| \						  CFG_OR_TIMING_FLASH	  \						)#define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \						  BR_MS_GPCM						| \						  BR_PS_8							| \						  BR_V 								  \						)/* * SDRAM configuration */#define CFG_OR1_AM	0xfc000000#define CFG_OR1		( (CFG_OR1_AM & OR_AM_MSK)	| \					  OR_CSNT_SAM				  \					)#define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \					  BR_MS_UPMA 				| \					  BR_PS_32	 				| \					  BR_V 						  \					)/* * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank * of 256 MBit SDRAM */#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16/* * Periodic timer for refresh @ 33 MHz system clock */#define CFG_MAMR_PTA	64/* * MAMR settings for SDRAM */#define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \						  MAMR_PTAE	    			| \						  MAMR_AMA_TYPE_1			| \						  MAMR_DSA_1_CYCL 			| \						  MAMR_G0CLA_A10			| \						  MAMR_RLFA_1X				| \						  MAMR_WLFA_1X				| \						  MAMR_TLFA_4X				  \						)/* * CS2* configuration for Disk On Chip: * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, * no burst. */#define CFG_OR2_PRELIM 	( (0xffff0000 & OR_AM_MSK)	| \						  OR_CSNT_SAM				| \						  OR_ACS_DIV2				| \						  OR_BI						| \						  OR_SCY_2_CLK				| \						  OR_TRLX					| \						  OR_EHTR					  \						)#define CFG_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \						  BR_PS_8					| \						  BR_MS_GPCM				| \						  BR_V						  \						)/* * CS3* configuration for FPGA: * 33 MHz bus with SCY=15, no burst. * The FPGA uses TA and TEA to terminate bus cycles, but we * clear SETA and set the cycle length to a large number so that * the cycle will still complete even if there is a configuration * error that prevents TA from asserting on FPGA accesss. */#define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \						  OR_SCY_15_CLK				| \						  OR_BI 					  \						)#define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \						  BR_PS_32					| \						  BR_MS_GPCM				| \						  BR_V		  				  \						)/* * CS4* configuration for FPGA SelectMap configuration interface. * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge * of GCLK1_50 */#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)  	| \						  OR_G5LS						| \						  OR_BI							  \						)#define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \						  BR_PS_8						| \						  BR_MS_UPMB					| \						  BR_V			  				  \						)/* * CS5* configuration for Mil-Std 1553 databus interface. * 33 MHz bus, GPCM, no burst. * The 1553 interface  uses TA and TEA to terminate bus cycles, * but we clear SETA and set the cycle length to a large number so that * the cycle will still complete even if there is a configuration * error that prevents TA from asserting on FPGA accesss. */#define CFG_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \						  OR_SCY_15_CLK				| \						  OR_EHTR					| \						  OR_TRLX					| \						  OR_CSNT_SAM				| \						  OR_BI						  \						)#define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \						  BR_PS_16					| \						  BR_MS_GPCM				| \						  BR_V			  			  \						)/* * Boot Flags */#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02	/* Software reboot					*//* * Disk On Chip (millenium) configuration */#if !defined(CONFIG_SC)#define CFG_MAX_DOC_DEVICE	1#undef	CFG_DOC_SUPPORT_2000#define CFG_DOC_SUPPORT_MILLENNIUM#undef	CFG_DOC_PASSIVE_PROBE#endif/* * FEC interrupt assignment */#define FEC_INTERRUPT   SIU_LEVEL1/* * Sanity checks */#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured#endif#endif	/* __CONFIG_GEN860T_H *//* vim: set ts=4 tw=78 ai shiftwidth=4: */