?? gt64260r.h
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/****************************************/#define CUNIT_ADDRESS 0xf340#define CUNIT_COMMAND_AND_ID 0xf344#define CUNIT_WRITE_DATA_LOW 0xf348#define CUNIT_WRITE_DATA_HIGH 0xf34c#define CUNIT_WRITE_BYTE_ENABLE 0xf358#define CUNIT_READ_DATA_LOW 0xf350#define CUNIT_READ_DATA_HIGH 0xf354#define CUNIT_READ_ID 0xf35c/****************************************//* Fast Ethernet Unit Registers *//****************************************//* Ethernet */#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000#define ETHERNET_SMI_REGISTER 0x2010/* Ethernet 0 */#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410#define ETHERNET0_PORT_STATUS_REGISTER 0x2418#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4/* Ethernet 1 */#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810#define ETHERNET1_PORT_STATUS_REGISTER 0x2818#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4#define ETHERNET1_MIB_COUNTER_BASE 0x2900/* Ethernet 2 */#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4#define ETHERNET2_MIB_COUNTER_BASE 0x2d00/****************************************//* SDMA Registers *//****************************************/#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0#define CHANNEL0_CONFIGURATION_REGISTER 0x4000#define CHANNEL0_COMMAND_REGISTER 0x4008#define CHANNEL0_RX_CMD_STATUS 0x4800#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804#define CHANNEL0_RX_BUFFER_POINTER 0x4808#define CHANNEL0_RX_NEXT_POINTER 0x480c#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810#define CHANNEL0_TX_CMD_STATUS 0x4C00#define CHANNEL0_TX_PACKET_SIZE 0x4C04#define CHANNEL0_TX_BUFFER_POINTER 0x4C08#define CHANNEL0_TX_NEXT_POINTER 0x4C0c#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14#define CHANNEL1_CONFIGURATION_REGISTER 0x5000#define CHANNEL1_COMMAND_REGISTER 0x5008#define CHANNEL1_RX_CMD_STATUS 0x5800#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804#define CHANNEL1_RX_BUFFER_POINTER 0x5808#define CHANNEL1_RX_NEXT_POINTER 0x580c#define CHANNEL1_TX_CMD_STATUS 0x5C00#define CHANNEL1_TX_PACKET_SIZE 0x5C04#define CHANNEL1_TX_BUFFER_POINTER 0x5C08#define CHANNEL1_TX_NEXT_POINTER 0x5C0c#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14#define CHANNEL2_CONFIGURATION_REGISTER 0x6000#define CHANNEL2_COMMAND_REGISTER 0x6008#define CHANNEL2_RX_CMD_STATUS 0x6800#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804#define CHANNEL2_RX_BUFFER_POINTER 0x6808#define CHANNEL2_RX_NEXT_POINTER 0x680c#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810#define CHANNEL2_TX_CMD_STATUS 0x6C00#define CHANNEL2_TX_PACKET_SIZE 0x6C04#define CHANNEL2_TX_BUFFER_POINTER 0x6C08#define CHANNEL2_TX_NEXT_POINTER 0x6C0c#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14/* SDMA Interrupt */#define SDMA_CAUSE 0xb820#define SDMA_MASK 0xb8a0/****************************************//* Baude Rate Generators Registers *//****************************************//* BRG 0 */#define BRG0_CONFIGURATION_REGISTER 0xb200#define BRG0_BAUDE_TUNING_REGISTER 0xb204/* BRG 1 */#define BRG1_CONFIGURATION_REGISTER 0xb208#define BRG1_BAUDE_TUNING_REGISTER 0xb20c/* BRG 2 */#define BRG2_CONFIGURATION_REGISTER 0xb210#define BRG2_BAUDE_TUNING_REGISTER 0xb214/* BRG Interrupts */#define BRG_CAUSE_REGISTER 0xb834#define BRG_MASK_REGISTER 0xb8b4/* MISC */#define MAIN_ROUTING_REGISTER 0xb400#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c#define WATCHDOG_CONFIGURATION_REGISTER 0xb410#define WATCHDOG_VALUE_REGISTER 0xb414/****************************************//* Flex TDM Registers *//****************************************//* FTDM Port */#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800#define FLEXTDM_RECEIVE_READ_POINTER 0xa804#define FLEXTDM_CONFIGURATION_REGISTER 0xa808#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818/* FTDM Interrupts */#define FTDM_CAUSE_REGISTER 0xb830#define FTDM_MASK_REGISTER 0xb8b0/****************************************//* GPP Interface Registers *//****************************************/#define GPP_IO_CONTROL 0xf100#define GPP_LEVEL_CONTROL 0xf110#define GPP_VALUE 0xf104#define GPP_INTERRUPT_CAUSE 0xf108#define GPP_INTERRUPT_MASK 0xf10c#define MPP_CONTROL0 0xf000#define MPP_CONTROL1 0xf004#define MPP_CONTROL2 0xf008#define MPP_CONTROL3 0xf00c#define DEBUG_PORT_MULTIPLEX 0xf014#define SERIAL_PORT_MULTIPLEX 0xf010/****************************************//* I2C Registers *//****************************************/#define I2C_SLAVE_ADDRESS 0xc000#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040#define I2C_DATA 0xc004#define I2C_CONTROL 0xc008#define I2C_STATUS_BAUDE_RATE 0xc00C#define I2C_SOFT_RESET 0xc01c/****************************************//* MPSC Registers *//****************************************//* MPSC0 */#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004#define MPSC0_PROTOCOL_CONFIGURATION 0x8008#define CHANNEL0_REGISTER1 0x800c#define CHANNEL0_REGISTER2 0x8010#define CHANNEL0_REGISTER3 0x8014#define CHANNEL0_REGISTER4 0x8018#define CHANNEL0_REGISTER5 0x801c#define CHANNEL0_REGISTER6 0x8020#define CHANNEL0_REGISTER7 0x8024#define CHANNEL0_REGISTER8 0x8028#define CHANNEL0_REGISTER9 0x802c#define CHANNEL0_REGISTER10 0x8030#define CHANNEL0_REGISTER11 0x8034/* MPSC1 */#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844#define MPSC1_PROTOCOL_CONFIGURATION 0x8848#define CHANNEL1_REGISTER1 0x884c#define CHANNEL1_REGISTER2 0x8850#define CHANNEL1_REGISTER3 0x8854#define CHANNEL1_REGISTER4 0x8858#define CHANNEL1_REGISTER5 0x885c#define CHANNEL1_REGISTER6 0x8860#define CHANNEL1_REGISTER7 0x8864#define CHANNEL1_REGISTER8 0x8868#define CHANNEL1_REGISTER9 0x886c#define CHANNEL1_REGISTER10 0x8870#define CHANNEL1_REGISTER11 0x8874/* MPSC2 */#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044#define MPSC2_PROTOCOL_CONFIGURATION 0x9048#define CHANNEL2_REGISTER1 0x904c#define CHANNEL2_REGISTER2 0x9050#define CHANNEL2_REGISTER3 0x9054#define CHANNEL2_REGISTER4 0x9058#define CHANNEL2_REGISTER5 0x905c#define CHANNEL2_REGISTER6 0x9060#define CHANNEL2_REGISTER7 0x9064#define CHANNEL2_REGISTER8 0x9068#define CHANNEL2_REGISTER9 0x906c#define CHANNEL2_REGISTER10 0x9070#define CHANNEL2_REGISTER11 0x9074/* MPSCs Interupts */#define MPSC0_CAUSE 0xb824#define MPSC0_MASK 0xb8a4#define MPSC1_CAUSE 0xb828#define MPSC1_MASK 0xb8a8#define MPSC2_CAUSE 0xb82c#define MPSC2_MASK 0xb8ac#endif /* __INCgt64260rh */?? 快捷鍵說明
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