*sdmr_ptr = sdmr | PSDMR_OP_MRW;	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;	*base = c;	/*	 * Check memory range for valid RAM. A simple memory test determines	 * the actually available RAM size between addresses `base' and	 * `base + maxsize'. Some (not all) hardware errors are detected:	 * - short between address lines	 * - short between data lines	 */	i = 0;	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {		addr = (volatile ulong *) base + cnt;	/* pointer arith! */		save[i++] = *addr;		*addr = ~cnt;	}	addr = (volatile ulong *) base;	save[i] = *addr;	*addr = 0;	if ((val = *addr) != 0) {		*addr = save[i];		return (0);	}	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {		addr = (volatile ulong *) base + cnt;	/* pointer arith! */		val = *addr;		*addr = save[--i];		if (val != ~cnt) {			/* Write the actual size to ORx			 */			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);			return (cnt * sizeof (long));		}	}	return (maxsize);}/* * Test Power-On-Reset. */int power_on_reset (void){	DECLARE_GLOBAL_DATA_PTR;	/* Test Reset Status Register */	return gd->reset_status & RSR_CSRS ? 0 : 1;}long int initdram (int board_type){	volatile immap_t *immap = (immap_t *) CFG_IMMR;	volatile memctl8260_t *memctl = &immap->im_memctl;#ifndef CFG_RAMBOOT	long size8, size9;#endif	long psize, lsize;	psize = 16 * 1024 * 1024;	lsize = 0;	memctl->memc_psrt = CFG_PSRT;	memctl->memc_mptpr = CFG_MPTPR;#if 0							/* Just for debugging */#define	prt_br_or(brX,orX) do {				\    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\    printf ("\n"					\	    #brX " 0x%08x  " #orX " 0x%08x "		\	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\	memctl->memc_ ## brX, memctl->memc_ ## orX,	\	start, start+sizem, (sizem+1)>>20);		\    } while (0)	prt_br_or (br0, or0);	prt_br_or (br1, or1);	prt_br_or (br2, or2);	prt_br_or (br3, or3);#endif#ifndef CFG_RAMBOOT	/* 60x SDRAM setup:	 */	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,					  (uchar *) CFG_SDRAM_BASE);	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,					  (uchar *) CFG_SDRAM_BASE);	if (size8 < size9) {		psize = size9;		printf ("(60x:9COL - %ld MB, ", psize >> 20);	} else {		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,						  (uchar *) CFG_SDRAM_BASE);		printf ("(60x:8COL - %ld MB, ", psize >> 20);	}	/* Local SDRAM setup:	 */#ifdef CFG_INIT_LOCAL_SDRAM	memctl->memc_lsrt = CFG_LSRT;	size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,					  (uchar *) SDRAM_BASE2_PRELIM);	size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,					  (uchar *) SDRAM_BASE2_PRELIM);	if (size8 < size9) {		lsize = size9;		printf ("Local:9COL - %ld MB) using ", lsize >> 20);	} else {		lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,						  (uchar *) SDRAM_BASE2_PRELIM);		printf ("Local:8COL - %ld MB) using ", lsize >> 20);	}#if 0	/* Set up BR2 so that the local SDRAM goes	 * right after the 60x SDRAM	 */	memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |			(CFG_SDRAM_BASE + psize);#endif#endif /* CFG_INIT_LOCAL_SDRAM */#endif /* CFG_RAMBOOT */	icache_enable ();	config_scoh_cs ();	return (psize);}/* ------------------------------------------------------------------------- */static void config_scoh_cs (void){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8260_t *memctl = &immr->im_memctl;	volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;	volatile uint tmp, i;	/* Initialize OR3 / BR3 for CAN Bus Controller 0 */	memctl->memc_or3 = CFG_CAN0_OR3;	memctl->memc_br3 = CFG_CAN0_BR3;	/* Initialize OR4 / BR4 for CAN Bus Controller 1 */	memctl->memc_or4 = CFG_CAN1_OR4;	memctl->memc_br4 = CFG_CAN1_BR4;	/* Initialize MAMR to write in the array at address 0x0 */	memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;	/* Initialize UPMA for CAN: single read */	memctl->memc_mdr = 0xcffeec00;	udelay (1);					/* Necessary to have the data correct in the UPM array!!!! */	/* The read on the CAN controller write the data of mdr in UPMA array. */	/* The index to the array will be incremented automatically	   through this read */	tmp = can->cpu_interface;	memctl->memc_mdr = 0x0ffcec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x0ffcec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x0ffcec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x0ffcec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x0ffcfc00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x0ffcfc00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0xfffdec07;	udelay (1);	tmp = can->cpu_interface;	/* Initialize MAMR to write in the array at address 0x18 */	memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;	/* Initialize UPMA for CAN: single write */	memctl->memc_mdr = 0xfcffec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x00ffec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x00ffec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x00ffec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x00ffec00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x00fffc00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x00fffc00;	udelay (1);	tmp = can->cpu_interface;	memctl->memc_mdr = 0x30ffec07;	udelay (1);	tmp = can->cpu_interface;	/* Initialize MAMR */	memctl->memc_mamr = MxMR_GPL_x4DIS;	/* GPL_B4 ouput line Disable */	/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */	memctl->memc_or5 = CFG_EXTPROM_OR5;	memctl->memc_br5 = CFG_EXTPROM_BR5;	/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */	memctl->memc_or6 = CFG_EXTPROM_OR6;	memctl->memc_br6 = CFG_EXTPROM_BR6;	/* Initialize OR7 / BR7 for the Glue Logic */	memctl->memc_or7 = CFG_FIOX_OR7;	memctl->memc_br7 = CFG_FIOX_BR7;	/* Initialize OR8 / BR8 for the DOH Logic */	memctl->memc_or8 = CFG_FDOHM_OR8;	memctl->memc_br8 = CFG_FDOHM_BR8;	DEBUGF ("OR0 %08x   BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);	DEBUGF ("OR1 %08x   BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);	DEBUGF ("OR2 %08x   BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);	DEBUGF ("OR3 %08x   BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);	DEBUGF ("OR4 %08x   BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);	DEBUGF ("OR5 %08x   BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);	DEBUGF ("OR6 %08x   BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);	DEBUGF ("OR7 %08x   BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);	DEBUGF ("OR8 %08x   BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);	DEBUGF ("UPMA  addr 0x0\n");	memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;	for (i = 0; i < 0x8; i++) {		tmp = can->cpu_interface;		udelay (1);		DEBUGF (" %08x ", memctl->memc_mdr);	}	DEBUGF ("\nUPMA  addr 0x18\n");	memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;	for (i = 0; i < 0x8; i++) {		tmp = can->cpu_interface;		udelay (1);		DEBUGF (" %08x ", memctl->memc_mdr);	}	DEBUGF ("\n");	memctl->memc_mamr = MxMR_GPL_x4DIS;}/* ------------------------------------------------------------------------- */int misc_init_r (void){	fpga_init ();	return (0);}/* ------------------------------------------------------------------------- */