#else# define SDRAM_MxMR_PTx         128# define UPM_MRS_ADDR           0x5# define UPM_REFRESH_ADDR       0x30#endif  /* !SDRAM_ALT_INIT_SEQUENCE */static const uint sdram_table[] ={	/* single read. (offset 0 in upm RAM) */	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,	0x1ff77c47,	/* precharge + MRS. (offset 5 in upm RAM) */	0x1ff77c34, 0xefeabc34, 0x1fb57c35,	/* burst read. (offset 8 in upm RAM) */	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/* single write. (offset 18 in upm RAM) */	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/* burst write. (offset 20 in upm RAM) */	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/* refresh. (offset 30 in upm RAM) */	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,	0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/* exception. (offset 3c in upm RAM) */	0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };/* ------------------------------------------------------------------------- */#else#error SDRAM not correctly configured#endif/* ------------------------------------------------------------------------- *//* * Memory Periodic Timer Prescaler */#define SDRAM_OR4VALUE   0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */#define SDRAM_BR4VALUE   0x000000c1 /* UPMB,base addr or'ed on later *//* ------------------------------------------------------------------------- */#ifdef SDRAM_ALT_INIT_SEQENCE/* ------------------------------------------------------------------------- */static int _initsdram(uint base, uint noMbytes){	volatile immap_t     *immap = (immap_t *)CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = SDRAM_MPTPRVALUE;	/* Configure the refresh (mostly).  This needs to be	* based upon processor clock speed and optimized to provide	* the highest level of performance.  For multiple banks,	* this time has to be divided by the number of banks.	* Although it is not clear anywhere, it appears the	* refresh steps through the chip selects for this UPM	* on each refresh cycle.	* We have to be careful changing	* UPM registers after we ask it to run these commands.	*/	memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */	memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */	udelay(200);	/* Now run the precharge/nop/mrs commands.	*/	memctl->memc_mcr = 0x80808111;   /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */	                                 /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */	udelay(200);	/* Run 8 refresh cycles */	memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/					    /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */	udelay(200);	memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */	memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */					    /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */	udelay(200);	memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);	memctl->memc_br4 = SDRAM_BR4VALUE | base;	return 0;}/* ------------------------------------------------------------------------- */#else  /* !SDRAM_ALT_INIT_SEQUENCE *//* ------------------------------------------------------------------------- *//* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */# define MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */# define MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   *//* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */# define MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */# define MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   *//* * MxMR settings for SDRAM *//* 8 column SDRAM */# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTBE  |   \			MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)/* 9 column SDRAM */# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTAE  |   \			MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)static int _initsdram(uint base, uint noMbytes){	volatile immap_t     *immap = (immap_t *)CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = MPTPR_2BK_4K;	memctl->memc_mbmr  = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */	/* map CS 4 */	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);	memctl->memc_br4 = SDRAM_BR4VALUE | base;	/* Perform SDRAM initilization */# ifdef UPM_NOP_ADDR    /* not currently in UPM table */	/* step 1: nop */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(0) | UPM_NOP_ADDR;# endif	/* step 2: delay */	udelay(200);# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */	/* step 3: precharge */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(4) | UPM_PRECHARGE_ADDR;# endif	/* step 4: refresh */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(2) | UPM_REFRESH_ADDR;	/*	 * note: for some reason, the UPM values we are using include	 * precharge with MRS	 */	/* step 5: mrs */	memctl->memc_mar = 0x00000088;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(1) | UPM_MRS_ADDR;# ifdef UPM_NOP_ADDR	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(0) | UPM_NOP_ADDR;# endif	/*	 * Enable refresh	 */	memctl->memc_mbmr |= MBMR_PTBE;	return 0;}#endif  /* !SDRAM_ALT_INIT_SEQUENCE *//* ------------------------------------------------------------------------- */static void _sdramdisable(void){	volatile immap_t     *immap = (immap_t *)CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	memctl->memc_br4 = 0x00000000;	/* maybe we should turn off upmb here or something */}/* ------------------------------------------------------------------------- */static int initsdram(uint base, uint *noMbytes){	uint m = CFG_SDRAM_SIZE>>20;	/* _initsdram needs access to sdram */	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */	if(!_initsdram(base, m))	{	        *noMbytes += m;		return 0;	}	else	{		*((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */		_sdramdisable();		return -1;	}}/* SDRAM SUPPORT (FADS ONLY) */#endif /* CONFIG_FADS */long int initdram (int board_type){	uint sdramsz = 0;	/* size of sdram in Mbytes */	uint base = 0;		/* base of dram in bytes */	uint m = 0;		/* size of dram in Mbytes */	uint k, s;#ifdef CONFIG_FADS	if (!initsdram (0x00000000, &sdramsz)) {		base = sdramsz << 20;		printf ("(%u MB SDRAM) ", sdramsz);	}#endif	k = (*((uint *) BCSR2) >> 23) & 0x0f;	switch (k & 0x3) {		/* "MCM36100 / MT8D132X" */	case 0x00:		m = 4;		break;		/* "MCM36800 / MT16D832X" */	case 0x01:		m = 32;		break;		/* "MCM36400 / MT8D432X" */	case 0x02:		m = 16;		break;		/* "MCM36200 / MT16D832X ?" */	case 0x03:		m = 8;		break;	}	switch (k >> 2) {	case 0x02:		k = 70;		break;	case 0x03:		k = 60;		break;	default:		printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);		k = 70;	}#ifdef CONFIG_FADS	/* the FADS is missing this bit, all rams treated as non-edo */	s = 0;#else	s = (*((uint *) BCSR2) >> 27) & 0x01;#endif	if (!_draminit (base, m, s, k)) {		printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");	} else {		_dramdisable ();		m = 0;	}	m += sdramsz;				/* add sdram size to total */	if (!m) {		/********************************		*DRAM ERROR, HALT PROCESSOR		*********************************/		while (1);		return -1;	}	return (m << 20);}/* ------------------------------------------------------------------------- */int testdram (void){    /* TODO: XXX XXX XXX */    printf ("test: 16 MB - ok\n");    return (0);}#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)#ifdef CFG_PCMCIA_MEM_ADDRvolatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;#endifint pcmcia_init(void){	volatile pcmconf8xx_t	*pcmp;	uint v, slota, slotb;	/*	** Enable the PCMCIA for a Flash card.	*/	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));#if 0	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;	pcmp->pcmc_por0 = 0xc00ff05d;#endif	/* Set all slots to zero by default. */	pcmp->pcmc_pgcra = 0;	pcmp->pcmc_pgcrb = 0;#ifdef PCMCIA_SLOT_A	pcmp->pcmc_pgcra = 0x40;#endif#ifdef PCMCIA_SLOT_B	pcmp->pcmc_pgcrb = 0x40;#endif	/* enable PCMCIA buffers */	*((uint *)BCSR1) &= ~BCSR1_PCCEN;	/* Check if any PCMCIA card is plugged in. */	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;	if (!(slota || slotb)) {		printf("No card present\n");#ifdef PCMCIA_SLOT_A		pcmp->pcmc_pgcra = 0;#endif#ifdef PCMCIA_SLOT_B		pcmp->pcmc_pgcrb = 0;#endif		return -1;	}	else		printf("Card present (");	v = 0;	/* both the ADS and the FADS have a 5V keyed pcmcia connector (?)	**	** Paolo - Yes, but i have to insert some 3.3V card in that slot on	**	   my FADS... :-)	*/#if defined(CONFIG_MPC86x)	switch ((pcmp->pcmc_pipr >> 30) & 3)#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)	switch ((pcmp->pcmc_pipr >> 14) & 3)#endif	{	case 0x00 :		printf("5V");		v = 5;		break;	case 0x01 :		printf("5V and 3V");#ifdef CONFIG_FADS		v = 3; /* User lower voltage if supported! */#else		v = 5;#endif		break;	case 0x03 :		printf("5V, 3V and x.xV");#ifdef CONFIG_FADS		v = 3; /* User lower voltage if supported! */#else		v = 5;#endif		break;	}	switch (v) {#ifdef CONFIG_FADS	case 3:		printf("; using 3V");		/*		** Enable 3 volt Vcc.		*/		*((uint *)BCSR1) &= ~BCSR1_PCCVCC1;		*((uint *)BCSR1) |= BCSR1_PCCVCC0;		break;#endif	case 5:		printf("; using 5V");#ifdef CONFIG_ADS		/*		** Enable 5 volt Vcc.		*/		*((uint *)BCSR1) &= ~BCSR1_PCCVCCON;#endif#ifdef CONFIG_FADS		/*		** Enable 5 volt Vcc.		*/		*((uint *)BCSR1) &= ~BCSR1_PCCVCC0;		*((uint *)BCSR1) |= BCSR1_PCCVCC1;#endif		break;	default:		*((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */		printf("; unknown voltage");		return -1;	}	printf(")\n");	/* disable pcmcia reset after a while */	udelay(20);#ifdef PCMCIA_SLOT_A	pcmp->pcmc_pgcra = 0;#elif PCMCIA_SLOT_B	pcmp->pcmc_pgcrb = 0;#endif	/* If you using a real hd you should give a short	* spin-up time. */#ifdef CONFIG_DISK_SPINUP_TIME	udelay(CONFIG_DISK_SPINUP_TIME);#endif	return 0;}#endif	/* CFG_CMD_PCMCIA *//* ------------------------------------------------------------------------- */#ifdef CFG_PC_IDE_RESETvoid ide_set_reset(int on){	volatile immap_t *immr = (immap_t *)CFG_IMMR;	/*	 * Configure PC for IDE Reset Pin	 */	if (on) {		/* assert RESET */		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);	} else {		/* release RESET */		immr->im_ioport.iop_pcdat |=   CFG_PC_IDE_RESET;	}	/* program port pin as GPIO output */	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);	immr->im_ioport.iop_pcso  &= ~(CFG_PC_IDE_RESET);	immr->im_ioport.iop_pcdir |=   CFG_PC_IDE_RESET;}#endif	/* CFG_PC_IDE_RESET *//* ------------------------------------------------------------------------- */