//-----------------------------------------------------------------------
// ti750.H - TI TLC16C750 Serial Port Driver with HDLC
//
// Author: Michael Denio
// Copyright 2001, 2003 by Texas Instruments, Inc.
//-----------------------------------------------------------------------

//
// Platform Configurations
//
// (These are identical to the MX driver since the LogicIO card can
// be used along with serial. Note the inherent possibility for EMIF
// setting conflict here. This needs to be addressed to allow better
// "plug and play" for multiple daughtercards.)
//

#ifdef DSK6711
#define HW_CE_VALUE     0x42340827
#define HW_CLOCKRATE    150
#endif

#ifdef DSK6713
#define HW_CE_VALUE     0x42340827
#define HW_CLOCKRATE    225
#endif

#ifdef TEB6416
#define HW_CE_VALUE     0xc43c502f
#define HW_CLOCKRATE    500
#endif

#ifdef DSK6416
#define HW_CE_VALUE     0xa23a4823
#define HW_CLOCKRATE    600
#endif

//
// Global Configurations
//

#define HW_CE_REG    ((unsigned int*)0x1800010)

#define HW_IVAL         6               // Hardware interrupt index
#define HW_IFLAG        (1<<(HW_IVAL))
#define ACE_PORT_BASE    0xa0300000
#define ACE_FIFO         64             // This is the FIFO size we use

#define SREG( reg ) (*(volatile UINT8 *)(ACE_PORT_BASE+reg))


// register definition offsets
#define UART_RBR        0x00            // receiver buffer register (read only) */
#define UART_THR        0x00            // transmit holding register
#define UART_BRDL       0x00            // baud rate divisor latch low
#define UART_IER        0x04            // interrupt enable register
#define UART_BRDH       0x04            // baud rate divisor latch high
#define UART_IIR        0x08            // interrupt ident. register
#define UART_FCR        0x08            // FIFO control register
#define UART_LCR        0x0C            // line control register
#define UART_MCR        0x10            // modem control register
#define UART_LSR        0x14            // line status register
#define UART_MSR        0x1C            // modem status register
// interrupt enable register definitions
#define TL16C750_IER_RX_AVAIL   0x01    // receive data available interrupt
#define TL16C750_IER_TX_READY   0x02    // transmit holding reg empty interrupt
#define TL16C750_IER_LINE_STAT  0x04    // line status interrupt
#define TL16C750_IER_MDM_STAT   0x08    // modem status interrupt
#define TL16C750_IER_SLEEP      0x10    // sleep mode enable
#define TL16C750_IER_LOW_POWER  0x20    // low power mode enable
// interrupt ID register
#define TL16C750_IIR_NOINT      0x01    // 0 when interrupt pending
#define TL16C750_IIR_INTID      0x0e    // 3-bit interrupt ID field
#define TL16C750_IIR_MS         0x00    // modem status int
#define TL16C750_IIR_THRE       0x02    // transmitter holding register empty int
#define TL16C750_IIR_RDA        0x04    // received data available int
#define TL16C750_IIR_RLS        0x06    // receiver line status int
#define TL16C750_IIR_TIMEOUT    0x0c    // character time-out int
#define TL16C750_IIR_BIGFIFO    0x20    // 64 byte FIFO enabled
#define TL16C750_IIR_FIFO_EN    0xc0    // FIFOs enabled
// FIFO control register definitions
#define TL16C750_FCR_FIFO_ON    0x01    // FIFO enable
#define TL16C750_FCR_RX_RESET   0x02    // Receiver FIFO reset
#define TL16C750_FCR_TX_RESET   0x04    // Transmit FIFO reset
#define TL16C750_FCR_DMA        0x08    // DMA mode select
#define TL16C750_FCR_BIG_FIFO   0x20    // 64 byte FIFO enable
#define TL16C750_FCR_TRIG_0     0x00    // trigger level 0
#define TL16C750_FCR_TRIG_1     0x40    // trigger level 1
#define TL16C750_FCR_TRIG_2     0x80    // trigger level 2
#define TL16C750_FCR_TRIG_3     0xc0    // trigger level 3
// Line control register definitions
#define TL16C750_LCR_LEN_5      0x00#define TL16C750_LCR_LEN_6      0x01#define TL16C750_LCR_LEN_7      0x02#define TL16C750_LCR_LEN_8      0x03#define TL16C750_LCR_STOP_1     0x00#define TL16C750_LCR_VARSTOP    0x04#define TL16C750_LCR_PAREN      0x08#define TL16C750_LCR_PAREVEN    0x10#define TL16C750_LCR_SPAR       0x20#define TL16C750_LCR_BREAK      0x40#define TL16C750_LCR_DLAB       0x80// Modem control register
#define TL16C750_MCR_DTR        0x01    // data terminal ready
#define TL16C750_MCR_RTS        0x02    // request to send
#define TL16C750_MCR_OUT1       0x04    // out1 signal
#define TL16C750_MCR_OUT2       0x08    // out2 signal
#define TL16C750_MCR_LOOP       0x10    // loopback
#define TL16C750_MCR_AFE        0x20    // autoflow control enable
// Line status register
#define TL16C750_LSR_DR         0x01    // data ready
#define TL16C750_LSR_OE         0x02    // overrun error
#define TL16C750_LSR_PE         0x04    // parity enable
#define TL16C750_LSR_FE         0x08    // framing error
#define TL16C750_LSR_BI         0x10    // break interrupt
#define TL16C750_LSR_THRE       0x20    // transmitter holding register empty
#define TL16C750_LSR_TEMT       0x40    // transmitter empty
#define TL16C750_LSR_FIFO_ERR   0x80    // error in receiver FIFO
// Modem status register
#define TL16C750_MSR_DCTS       0x01    // delta clear to send
#define TL16C750_MSR_DDSR       0x02    // delta data set ready
#define TL16C750_MSR_TERI       0x04    // trailing edge ring indicator
#define TL16C750_MSR_DDCD       0x08    // delta data carrier detect
#define TL16C750_MSR_CTS        0x10    // clear to send
#define TL16C750_MSR_DSR        0x20    // data set ready
#define TL16C750_MSR_RI         0x40    // ring indicator
#define TL16C750_MSR_DCD        0x80    // data carrier detect