//-----------------------------------------------------------------------
// ti752.h - TI TLC16C752 Serial Port Driver with HDLC
//
// Author: Michael Denio
// Copyright 2001, 2004 by Texas Instruments, Inc.
//-----------------------------------------------------------------------

//
// Platform Configurations
//

#ifdef EVMDM642
#include "..\..\..\example\tools\common\evmdm642_osd\evmdm642_osd.h"
#define HW_CE_VALUE     0x73a78e01
#define HW_CLOCKRATE    600
#define HW_CE_REG       ((unsigned int*)0x1800004)
#define ACE_PORT_BASE1  0x90080000
#define ACE_PORT_BASE2  0x90080008
#define BAUDRATENUM     1843200         // Divide this by BAUD to get divider
#endif

//
// Global Configurations
//

#define HW_IVAL         7               // Hardware interrupt index
#define HW_IFLAG        (1<<(HW_IVAL))
#define ACE_FIFO        64              // This is the FIFO size we use

#define SREG( pi, r ) (*(volatile UINT8 *)((pi->HwBaseAddr)+r))

// register definition offsets
#define UART_RBR        0x00            // receiver buffer register (read only)
#define UART_THR        0x00            // transmit holding register
#define UART_BRDL       0x00            // baud rate divisor latch low
#define UART_IER        0x01            // interrupt enable register
#define UART_BRDH       0x01            // baud rate divisor latch high
#define UART_IIR        0x02            // interrupt ident. register
#define UART_FCR        0x02            // FIFO control register
#define UART_EFR        0x02            // Ehanced feature register
#define UART_LCR        0x03            // line control register
#define UART_MCR        0x04            // modem control register
#define UART_LSR        0x05            // line status register
#define UART_MSR        0x06            // modem status register
#define UART_TCR        0x06            // transmission control register
#define UART_TLR        0x07            // trigger level register

// interrupt enable register definitions
#define TL16C752_IER_RX_AVAIL   0x01    // receive data available interrupt
#define TL16C752_IER_TX_READY   0x02    // transmit holding reg empty interrupt
#define TL16C752_IER_LINE_STAT  0x04    // line status interrupt
#define TL16C752_IER_MDM_STAT   0x08    // modem status interrupt
#define TL16C752_IER_SLEEP      0x10    // sleep mode enable
#define TL16C752_IER_XOFF       0x20    // xoff interrupt
#define TL16C752_IER_RTS        0x40    // rts interrupt
#define TL16C752_IER_CTS        0x80    // cts interrupt
// interrupt ID register
#define TL16C752_IIR_NOINT      0x01    // 0 when interrupt pending
#define TL16C752_IIR_INTID      0x0e    // 3-bit interrupt ID field
#define TL16C752_IIR_MS         0x00    // modem status int
#define TL16C752_IIR_THRE       0x02    // transmitter holding register empty int
#define TL16C752_IIR_RDA        0x04    // received data available int
#define TL16C752_IIR_RLS        0x06    // receiver line status int
#define TL16C752_IIR_TIMEOUT    0x0c    // character time-out int
#define TL16C752_IIR_XOFF       0x10    // Received Xoff
#define TL16C752_IIR_CTSRTS     0x20    // CTS / RTS change
// FIFO control register definitions
#define TL16C752_FCR_FIFO_ON    0x01    // FIFO enable
#define TL16C752_FCR_RX_RESET   0x02    // Receiver FIFO reset
#define TL16C752_FCR_TX_RESET   0x04    // Transmit FIFO reset
#define TL16C752_FCR_DMA        0x08    // DMA mode select
#define TL16C752_FCR_TX_TRIG_8  0x00    // tx trigger level 8 spaces
#define TL16C752_FCR_TX_TRIG_16 0x10    // tx trigger level 16 spaces
#define TL16C752_FCR_TX_TRIG_32 0x20    // tx trigger level 32 spaces
#define TL16C752_FCR_TX_TRIG_56 0x30    // tx trigger level 56 spaces
#define TL16C752_FCR_RX_TRIG_8  0x00    // rx trigger level 8 spaces
#define TL16C752_FCR_RX_TRIG_16 0x40    // rx trigger level 16 spaces
#define TL16C752_FCR_RX_TRIG_56 0x80    // rx trigger level 56 spaces
#define TL16C752_FCR_RX_TRIG_60 0xc0    // rx trigger level 60 spaces
// Line control register definitions
#define TL16C752_LCR_LEN_5      0x00#define TL16C752_LCR_LEN_6      0x01#define TL16C752_LCR_LEN_7      0x02#define TL16C752_LCR_LEN_8      0x03#define TL16C752_LCR_STOP_1     0x00#define TL16C752_LCR_VARSTOP    0x04#define TL16C752_LCR_PAREN      0x08#define TL16C752_LCR_PAREVEN    0x10#define TL16C752_LCR_SPAR       0x20#define TL16C752_LCR_BREAK      0x40#define TL16C752_LCR_DLABEFR    0x80// Modem control register
#define TL16C752_MCR_DTR        0x01    // data terminal ready
#define TL16C752_MCR_RTS        0x02    // request to send
#define TL16C752_MCR_FIFORDY    0x04    // enable FIFO Rdy register
#define TL16C752_MCR_IRQEN      0x08    // enable IRQ output
#define TL16C752_MCR_LOOP       0x10    // loopback
#define TL16C752_MCR_XONANY     0x20    // Enable XON Any Func
#define TL16C752_MCR_TCRTLR     0x40    // enable TCR and TLR registers
#define TL16C752_MCR_CLKDIV4    0x80    // divide input clock by 4
// Line status register
#define TL16C752_LSR_DR         0x01    // data ready
#define TL16C752_LSR_OE         0x02    // overrun error
#define TL16C752_LSR_PE         0x04    // parity error
#define TL16C752_LSR_FE         0x08    // framing error
#define TL16C752_LSR_BI         0x10    // break interrupt
#define TL16C752_LSR_THRE       0x20    // transmitter holding register empty
#define TL16C752_LSR_TEMT       0x40    // transmitter empty
#define TL16C752_LSR_FIFO_ERR   0x80    // error in receiver FIFO
// Modem status register
#define TL16C752_MSR_DCTS       0x01    // delta clear to send
#define TL16C752_MSR_DDSR       0x02    // delta data set ready
#define TL16C752_MSR_TERI       0x04    // trailing edge ring indicator
#define TL16C752_MSR_DDCD       0x08    // delta data carrier detect
#define TL16C752_MSR_CTS        0x10    // clear to send
#define TL16C752_MSR_DSR        0x20    // data set ready
#define TL16C752_MSR_RI         0x40    // ring indicator
#define TL16C752_MSR_DCD        0x80    // data carrier detect
// Enhanced feature register definitions
#define TL16C752_EFR_SWFLOW     0x0F    // Software flow control modes
#define TL16C752_EFR_ENHANCE    0x10    // Enable enhanced functions
#define TL16C752_EFR_SPCHAR     0x20    // Special character detect
#define TL16C752_EFR_RTSFLOW    0x40    // RTS Flow control enabled
#define TL16C752_EFR_CTSFLOW    0x80    // CTS Flow control enabled