/* ataDrv.h - ATA/IDE (LOCAL and PCMCIA) disk controller header */#ifndef __INCpcataDrvh#define __INCpcataDrvh#ifdef __cplusplusextern "C" {#endif#ifndef _ASMLANGUAGE#include "dosFsLib.h"#include "blkIo.h"#include "wdLib.h"#include "private/semLibP.h"#include "drv/pcmcia/pccardLib.h"IMPORT ATA_RESOURCE ataResources[];/* define swap macro for little/big endian machines */#if _BYTE_ORDER == _BIG_ENDIAN#   define ATA_SWAP(x) LONGSWAP(x)#else#   define ATA_SWAP(x) (x)#endif#define IDE_LOCAL		0 	/* ctrl type: LOCAL(IDE) */#define ATA_PCMCIA		1	/* ctrl type: PCMCIA */#define ATA_MAX_CTRLS		1	/* max number of ATA controller */#define ATA_MAX_DRIVES		2	/* max number of ATA drives */typedef struct ataParams     {    short config;		/* general configuration */    short cylinders;		/* number of cylinders */    short removcyl;		/* number of removable cylinders */    short heads;		/* number of heads */    short bytesTrack;		/* number of unformatted bytes/track */    short bytesSec;		/* number of unformatted bytes/sector */    short sectors;		/* number of sectors/track */    short bytesGap;		/* minimum bytes in intersector gap */    short bytesSync;		/* minimum bytes in sync field */    short vendstat;		/* number of words of vendor status */    char  serial[20];		/* controller serial number */    short type;			/* controller type */    short size;			/* sector buffer size, in sectors */    short bytesEcc;		/* ecc bytes appended */    char  rev[8];		/* firmware revision */    char  model[40];		/* model name */    short multiSecs;		/* RW multiple support. bits 7-0 ia max secs */    short reserved48;		/* reserved */    short capabilities;		/* capabilities */    short reserved50;		/* reserved */    short pioMode;		/* PIO data transfer cycle timing mode */    short dmaMode;		/* single word DMA data transfer cycle timing */    short valid;		/* field validity */    short currentCylinders;	/* number of current logical cylinders */    short currentHeads;		/* number of current logical heads */    short currentSectors;	/* number of current logical sectors / track */    short capacity0;		/* current capacity in sectors */    short capacity1;		/* current capacity in sectors */    short multiSet;		/* multiple sector setting */    short sectors0;		/* total number of user addressable sectors */    short sectors1;		/* total number of user addressable sectors */    short singleDma;		/* single word DMA transfer */    short multiDma;		/* multi word DMA transfer */    short advancedPio;		/* flow control PIO transfer modes supported */    short cycletimeDma;		/* minimum multiword DMA transfer cycle time */    short cycletimeMulti;	/* recommended multiword DMA cycle time */    short cycletimePioNoIordy;	/* min PIO transfer cycle time wo flow ctl */    short cycletimePioIordy;	/* min PIO transfer cycle time w IORDY */    short reserved69;		/* reserved */    short reserved70;		/* reserved */    /* ATAPI */    short pktCmdRelTime;	/* [71]Typical Time for Release after Packet */    short servCmdRelTime;	/* [72]Typical Time for Release after SERVICE */    short majorRevNum;		/* [73] Major Revision Number (0|FFFF if no) */    short minorVersNum;		/* [74] Minor  Version Number (0|FFFF if no) */    short reserved75[53];	/* reserved */    short vendor[32];		/* vendor specific */    short reserved160[96];	/* reserved */    } ATA_PARAM;typedef enum /* ATAPI */    {    NON_DATA, /* non data command */    OUT_DATA,    IN_DATA    } t_data_dir;/* Device types */#define ATA_TYPE_NONE		0x00	/* device is faulty or not present */#define ATA_TYPE_ATA		0x01	/* ATA device */#define ATA_TYPE_ATAPI		0x02	/* ATAPI device */#define ATA_TYPE_INIT		255	/* device must be identified *//* Device  states */#define ATA_DEV_OK	0	/* device is OK */#define ATA_DEV_NONE	1	/* device absent or does not respond */#define ATA_DEV_DIAG_F	2	/* device diagnostic failed */#define ATA_DEV_PREAD_F	3	/* read device parameters failed */#define ATA_DEV_MED_CH	4	/* medium have been changed */#define ATA_DEV_NO_BLKDEV	5	/* No block device available */#define ATA_DEV_INIT	255	/* uninitialized device */typedef struct ataDev    {    BLK_DEV     blkDev;		/* must be here */    int         ctrl;		/* ctrl no.  0 - 1 */    int         drive;		/* drive no. 0 - 1 */    int         blkOffset;	/* sector offset */    int		nBlocks;	/* number of sectors */    char *	pBuf;		/* Current position in an user buffer */    char *	pBufEnd;	/* End of user buffer */    t_data_dir	direction;	/* Transfer direction */    int		transCount;	/* Number of transfer cycles */    int		errNum;		/* Error description message number */    /* ATAPI Registers contents */    uint8_t	intReason;	/* Interrupt Reason Register */    uint8_t	status;		/* Status Register */    uint16_t	transSize;	/* Byte Count Register */    } ATA_DEV;typedef struct ataDrive    {    ATA_PARAM	param;		/* geometry parameter */    short	okMulti;	/* MULTI: TRUE if supported */    short	okIordy;	/* IORDY: TRUE if supported */    short	okDma;		/* DMA:   TRUE if supported */    short	okLba;		/* LBA:   TRUE if supported */    short	multiSecs;	/* supported max sectors for multiple RW */    short	pioMode;	/* supported max PIO mode */    short	singleDmaMode;	/* supported max single word DMA mode */    short	multiDmaMode;	/* supported max multi word DMA mode */    short	rwMode;		/* RW mode: PIO[0,1,2,3,4] or DMA[0,1,2] */    short	rwBits;		/* RW bits: 16 or 32 */    short	rwPio;		/* RW PIO unit: single or multi sector */    short	rwDma;		/* RW DMA unit: single or multi word */    uint8_t	state;		/* device state */    uint8_t	diagCode;	/* diagnostic code */    uint8_t	type;		/* device type */    STATUS      (*Reset)	/* pointer to reset function */        (        int ctrl,        int dev        );    ATA_DEV     *pAtaDev;	/* pointer to ATA block device structure */    } ATA_DRIVE;typedef struct ataCtrl    {    ATA_DRIVE	drive[ATA_MAX_DRIVES];	/* drives per controller */    SEMAPHORE	syncSem;	/* binary sem for syncronization */    SEMAPHORE	muteSem;	/* mutex  sem for mutual-exclusion */    WDOG_ID	wdgId;		/* watch dog */    BOOL	wdgOkay;	/* watch dog status */    int		semTimeout;	/* timeout seconds for sync semaphore */    int		wdgTimeout;	/* timeout seconds for watch dog */    int		ctrlType;	/* type of controller */    BOOL	installed;	/* TRUE if a driver is installed */    BOOL	changed;	/* TRUE if a card is installed */    int		intLevel;	/* interrupt level */    int		intCount;	/* interrupt count */    int		intStatus;	/* interrupt status */    int		drives;		/* number of drives in the controller */    UINT32	data;		/* (RW) data register (16 bits)	*/    UINT32	error;		/* (R)  error register		*/    UINT32	feature;	/* (W)  feature or write-precompensation */    UINT32	seccnt;		/* (RW) sector count		*/    UINT32	sector;		/* (RW) first sector number	*/    UINT32	cylLo;		/* (RW) cylinder low byte	*/    UINT32	cylHi;		/* (RW) cylinder high byte	*/    UINT32	sdh;		/* (RW) sector size/drive/head	*/    UINT32	command;	/* (W)  command register	*/    UINT32	status;		/* (R)  immediate status	*/    UINT32	aStatus;	/* (R)  alternate status	*/    UINT32	dControl;	/* (W)  disk controller control	*/    UINT32	dAddress;	/* (R)  disk controller address */    int		configType;	/* or'd configuration flags     */    } ATA_CTRL;typedef struct ataType    {    int cylinders;		/* number of cylinders */    int heads;			/* number of heads */    int sectors;		/* number of sectors per track */    int bytes;			/* number of bytes per sector */    int precomp;		/* precompensation cylinder */    } ATA_TYPE;typedef struct ataRaw    {				/* this is for ATARAWACCESS ioctl */    UINT cylinder;		/* cylinder (0 -> (cylindres-1)) */    UINT head;			/* head (0 -> (heads-1)) */    UINT sector;		/* sector (1 -> sectorsTrack) */    char *pBuf;			/* pointer to buffer (bytesSector * nSecs) */    UINT nSecs;			/* number of sectors (1 -> sectorsTrack) */    UINT direction;		/* read=0, write=1 */    } ATA_RAW;#define ATA_SEM_TIMEOUT_DEF	5       /* default timeout for ATA sync sem */#define ATA_WDG_TIMEOUT_DEF	5       /* default timeout for ATA watch dog *//* ATA registers */#define	ATA_DATA(base0)		(base0 + 0x60) /* (RW) data register (16 bits) */#define ATA_ERROR(base0)	(base0 + 0x64) /* (R)  error register	    */#define	ATA_FEATURE(base0)	(base0 + 0x64) /* (W)  feature/precompensation */#define	ATA_SECCNT(base0)	(base0 + 0x68) /* (RW) sector count	    */#define	ATA_SECTOR(base0)	(base0 + 0x6C) /* (RW) first sector number	    */#define	ATA_CYL_LO(base0)	(base0 + 0x70) /* (RW) cylinder low byte	    */#define	ATA_CYL_HI(base0)	(base0 + 0x74) /* (RW) cylinder high byte	    */#define	ATA_SDH(base0)		(base0 + 0x78) /* (RW) sector size/drive/head  */#define	ATA_COMMAND(base0)	(base0 + 0x7C) /* (W)  command register	    */#define	ATA_STATUS(base0) 	(base0 + 0x5C) /* (R)  immediate status	    */#define	ATA_A_STATUS(base0)	(base0 + 0x5C) /* (R)  alternate status	    */#define	ATA_D_CONTROL(base0)	(base0 + 0x5C) /* (W)  disk controller control */#define	ATA_D_ADDRESS(base0)	(base0 + 0x5C) /* (R)  disk controller address *//* diagnostic code */#define ATA_DIAG_OK		0x01/* control register */#define ATA_CTL_4BIT	 	0x8	/* use 4 head bits (wd1003) */#define ATA_CTL_RST 		0x4	/* reset controller */#define ATA_CTL_IDS 		0x2	/* disable interrupts *//* status register */#define ATA_STAT_ACCESS		(ATA_STAT_BUSY | ATA_STAT_DRQ)					/* device accessible */#define	ATA_STAT_BUSY		0x80	/* controller busy */#define	ATA_STAT_READY		0x40	/* selected drive ready */#define	ATA_STAT_WRTFLT		0x20	/* write fault */#define	ATA_STAT_SEEKCMPLT	0x10	/* seek complete */#define	ATA_STAT_DRQ		0x08	/* data request */#define	ATA_STAT_ECCCOR		0x04	/* ECC correction made in data */