/***************************************************************************** sysClearSegs - clearing all the SEG's register.** This routine will zero the SEG's register.** SYNOPSIS* \ss* void sysClearSegs*     (*     void*     )* \se** RETURNS: N/A*/FUNC_BEGIN(sysClearSegs)	/* Init the Segment registers */	xor	r3, r3, r3        isync        mtsr    0,r3        mtsr    1,r3        mtsr    2,r3        mtsr    3,r3        mtsr    4,r3        mtsr    5,r3        mtsr    6,r3        mtsr    7,r3        mtsr    8,r3        mtsr    9,r3        mtsr    10,r3        mtsr    11,r3        mtsr    12,r3        mtsr    13,r3        mtsr    14,r3        mtsr    15,r3        isync	blrFUNC_END(sysClearSegs)/***************************************************************************** sysInvalidateTLBs - invalidate all the BAT's register** This routine will invalidate the BAT's register.** SYNOPSIS* \ss* void sysInvalidateTLBs*     (*     void*     )* \se** SEE ALSO: sysClearBATs(), sysClearBATsInvalidateTLBs(), sysMinimumBATsInit()** RETURNS: N/A*/FUNC_BEGIN(sysInvalidateTLBs)	isync	/* invalidate entries within both TLBs */	li	r3,128	mtctr	r3		/* CTR = 32  */	xor	r3,r3,r3	/* r3 = 0    */	isync			/* context sync req'd before tlbie */tlbloop:	tlbie	r3	sync			/* sync instr req'd after tlbie      */	addi	r3,r3,0x1000	/* increment bits 15-19 */	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */	isync	blrFUNC_END(sysInvalidateTLBs)/***************************************************************************** sysMinimumBATsInit - initialize the minimum BAT's register** This routine will initialize the minimum BAT's register.** SYNOPSIS* \ss* void sysMinimumBATsInit*     (*     void*     )* \se** NOTE: When the MMU is disabled, the processor is said to be in Real Addressing *       Mode. In this mode, all memory accesses are governed by a default set of *       bit values for the WIMG attribute bits. For data accesses, the default *       WIMG = 0011 and for instruction fetches default WIMG=0001. In both cases, *       the guarded (G) bit is set and the cache-inhibit (I) bit is clear. In *       other words, in real addressing mode, the entire address space of the *       processor is cacheable ("NOT cache-inhibited") and guarded -- independent *       of whether the caches are enabled or not.**       The guarded attribute merely prevents out-of-order and speculative *       *loads*. More details are avalible in section 5.2.1.5 of the PowerPC *       programming environments manual for a more complete explanation of the *       guarded attribute. While guarded is a necessary condition for those *       memory spaces in which devices reside, it is not a sufficient condition. *       Memory accesses to devices must be both guarded and cache inhibited. *       Physically disabling the data cache does not provide this second, *       equally necessary, condition.**       Above, I used the term "NOT cache-inhibited" to draw attention to an *       important distinction between cache-inhibited memory accesses and *       cacheable memory accesses that are made while the cache itself is *       disabled. A naive interpretation of "cacheability" holds that these two *       concepts are equivalent -- they are not. To prevent out-of-order *       *stores* to devices, we must mark the memory addresses at which those *       devices reside as cache inhibited. The only way to do this is to enable *       the MMU. So it holds that in order to enforce in-order loads AND stores, *       we must enable the MMU and mark the appropriate memory regions as CI & G.** SEE ALSO: sysClearBATs(), sysInvalidateTLBs(), sysClearBATsInvalidateTLBs()** RETURNS: N/A*/FUNC_BEGIN(sysMinimumBATsInit)	lis     r3, HI(0x00000032)	ori     r3, r3, LO(0x00000032)	sync	mtspr	DBAT0L,r3			isync	lis     r3, HI(0x000007FF)	/* SDRAM (64M block) */ 	ori     r3, r3, LO(0x000007FF)	sync	mtspr	DBAT0U,r3			isync	lis     r3, HI(0xF000002A)			ori     r3, r3, LO(0xF000002A)	sync	mtspr	DBAT1L,r3			isync	lis     r3, HI(0xF0001FFF)	/* Pheripherals (256M block) */	ori     r3, r3, LO(0xF0001FFF)	/* (eeprom,serial,ictrl)    */	sync				/* (PCI register space)     */	mtspr	DBAT1U,r3			isync	lis     r3, HI(0x8000002A)			ori     r3, r3, LO(0x8000002A)	sync	mtspr	DBAT2L,r3			isync	lis     r3, HI(0x800001FF)	/* 0x80000000 (16M block) */	ori     r3, r3, LO(0x800001FF)	sync	mtspr	DBAT2U,r3			isync	/* Turn on Data Relocation */	sync	mfmsr	r3	ori     r3, r3, _PPC_MSR_DR	sync	mtmsr   r3	isync	blrFUNC_END(sysMinimumBATsInit)/*********************************************************************** General system Input/Output ASM Routines** If  INCLUDE_C_IO_ROUTINES is not defined, then it is assumed these * routines are supplied in assembler code ( typically in sysALib.s ).**/#ifndef INCLUDE_C_IO_ROUTINES/***************************************************************************** sysPciInByte - reads a byte from PCI Config Space.** This function reads a byte from a specified PCI Config Space address.** SYNOPSIS* \ss* UCHAR sysPciInByte*     (*     ULONG address*     )* \se** SEE ALSO: sysPciInWord(), sysPciInLong(), sysPciOutByte(), sysPciOutWord(), *           sysPciOutLong()** RETURNS: byte from address.*/FUNC_BEGIN(sysInByte)FUNC_BEGIN(sysPciInByte)	lbzx	r3,r0,r3	/* Read byte from PCI space */	sync	bclr	20,0		/* Return to caller */FUNC_END(sysPciInByte)FUNC_END(sysInByte)/***************************************************************************** sysPciOutByte - writes a byte to PCI Config Space.** This function writes a byte to a specified PCI Config Space address.** SYNOPSIS* \ss* void sysPciOutByte*     (*     ULONG address*     UCHAR data*     )* \se** SEE ALSO: sysPciInByte(), sysPciInWord(), sysPciInLong(), sysPciOutWord(), *           sysPciOutLong()** RETURNS: N/A*/FUNC_BEGIN(sysOutByte)FUNC_BEGIN(sysPciOutByte)	stbx	r4,r0,r3	/* Write a byte to PCI space */	sync	bclr	20,0		/* Return to caller */FUNC_END(sysPciOutByte)FUNC_END(sysOutByte)/***************************************************************************** sysPciInWord - reads a word (16-bit big-endian) from PCI Config Space.** This function reads a word from a specified PCI Config Space (little-endian)* address.  It uses the load halfword byte-reversed instruction.** SYNOPSIS* \ss* USHORT sysPciInWord*     (*     ULONG address*     )* \se** SEE ALSO: sysPciInByte(), sysPciInLong(), sysPciOutByte(), sysPciOutWord(), *           sysPciOutLong()** RETURNS: word (16-bit big-endian) from address.*/FUNC_BEGIN(sysInWord)FUNC_BEGIN(sysPciInWord)	lhbrx   r3,r0,r3	/* Read and swap */	sync	bclr	20,0FUNC_END(sysPciInWord)FUNC_END(sysInWord)/***************************************************************************** sysPciOutWord - writes a word (16-bit big-endian) to PCI Config Space.** This function writes a word to a specified PCI Config Space (little-endian)* address.  It uses the store halfword byte-reversed instruction.** SYNOPSIS* \ss* void sysPciOutWord*     (*     ULONG  address*     USHORT data*     )* \se** SEE ALSO: sysPciInByte(), sysPciInWord(), sysPciInLong(), sysPciOutByte(), *           sysPciOutLong()** RETURNS: N/A*/FUNC_BEGIN(sysOutWord)FUNC_BEGIN(sysPciOutWord)	sthbrx  r4,r0,r3	/* Write with swap to address */	sync	bclr    20,0		/* Return to caller */FUNC_END(sysPciOutWord)FUNC_END(sysOutWord)/***************************************************************************** sysPciInLong - reads a long (32-bit big-endian) from PCI Config Space.** This function reads a long from a specified PCI Config Space (little-endian)* address.  It uses the load word byte-reversed instruction.** SYNOPSIS* \ss* ULONG sysPciInLong*     (*     ULONG address*     )* \se** SEE ALSO: sysPciInByte(), sysPciInWord(), sysPciOutByte(), sysPciOutWord(), *           sysPciOutLong()** RETURNS: long (32-bit big-endian) from address.*/FUNC_BEGIN(sysInLong)FUNC_BEGIN(sysPciInLong)	lwbrx   r3,r0,r3	/* Read and swap from address */	sync	bclr    20,0		/* Return to caller */FUNC_END(sysPciInLong)FUNC_END(sysInLong)/***************************************************************************** sysPciOutLong - writes a long (32-bit big-endian) to PCI Config Space.** This function writes a long to a specified PCI Config Space (little-endian)* address.  It uses the store word byte-reversed instruction.** SYNOPSIS* \ss* void sysPciOutLong*     (*     ULONG address*     ULONG data*     )* \se** SEE ALSO: sysPciInByte(), sysPciInWord(), sysPciInLong(), sysPciOutWord(), *           sysPciOutByte()** RETURNS: N/A*/FUNC_BEGIN(sysOutLong)FUNC_BEGIN(sysPciOutLong)	stwbrx  r4,r0,r3	/* store data as little-endian */	sync	bclr    20,0FUNC_END(sysPciOutLong)FUNC_END(sysOutLong)#endif /* INCLUDE_C_IO_ROUTINES */