/* m5200b.h - Motorola MPC5200B CPU control registers */

/*
This file contains I/O addresses and related constants for the MPC5200B
*/

#ifndef __INCmpc5200b
#define __INCmpc5200b

#ifdef __cplusplus
extern "C" {
#endif

#define MBAR_SIZE				0x40000	/* 256 KB */
#define MBAR_RESET_VALUE		0x80000000

#define MPC5200B_PCI_DEVICE_ID	0x5809
#define MPC5200B_PCI_VENDOR_ID	0x1057
#define MPC5200B_PCI_ID			((MPC5200B_PCI_DEVICE_ID << 16) | MPC5200B_PCI_VENDOR_ID)

/*-----------------------------------------------------------*/
/* IPBI Peripheral registers 						  0x0000 */
/*-----------------------------------------------------------*/

/* MBAR to IPBI */
#define MBAR_IPBI				0x0000

#define IPBI_CS0_START_OFF		0x0004
#define IPBI_CS0_STOP_OFF		0x0008
#define IPBI_CTRL_OFF			0x0054

#define IPBI_SDRAM_CONF0_OFF	0x0034
#define IPBI_SDRAM_CONF1_OFF	0x0038

#define IPBI_CTRL_CSBOOT		0x02000000
#define IPBI_CTRL_CS0			0x00010000
#define IPBI_CTRL_WSE			0x00000001

/*-----------------------------------------------------------*/
/* SDRAM											  0x0100 */
/*-----------------------------------------------------------*/

/* MBAR to LPC */
#define MBAR_SDRAM			0x0100

#define SDRAM_MODE_OFF		0x0000
#define SDRAM_CTRL_OFF		0x0004
#define SDRAM_CONF1_OFF		0x0008
#define SDRAM_CONF2_OFF		0x000C
#define SDRAM_SDELAY_OFF	0x0090

/*-----------------------------------------------------------*/
/* Clock Distribution Module (CDM)                    0x0200 */
/*-----------------------------------------------------------*/

/* MBAR to CDM */
#define MBAR_CDM			0x0200

#define CDM_PORSTCFG_OFF	0x0004	/* CDM Power On Reset Configuration Register */
#define CDM_BREAD_CRUM_OFF	0x0008	/* CDM Bread Crumb Register */
#define CDM_CFG_OFF			0x000C	/* CDM Configuration Register */
#define CDM_DIVIDER_OFF		0x0010	/* CDM 48MHz Fractional Divider Configuration Register */
#define CDM_CLK_ENABLE_OFF	0x0014	/* CDM Clock Enable Register */
#define CDM_OSC_CONFIG_OFF	0x0018	/* CDM System Oscillator Configuration Register */
#define CDM_PSC1_MCLOCK_OFF	0x0028	/* CDM PSC1 Mclock Config */
#define CDM_PSC2_MCLOCK_OFF	0x002C	/* CDM PSC2 Mclock Config */
#define CDM_PSC3_MCLOCK_OFF	0x0030	/* CDM PSC3 Mclock Config */
#define CDM_PSC6_MCLOCK_OFF	0x0034	/* CDM PSC6 Mclock Config */
	
#define CDM_BASE_ADRS		(MBAR_VALUE + MBAR_CDM)

#define CDM_PORSTCFG   		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_PORSTCFG_OFF   ))
#define CDM_BREAD_CRUM 		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_BREAD_CRUM_OFF ))
#define CDM_CFG        		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_CFG_OFF        ))
#define CDM_DIVIDER    		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_DIVIDER_OFF    ))
#define CDM_CLK_ENABLE 		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_CLK_ENABLE_OFF ))
#define CDM_OSC_CONFIG 		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_OSC_CONFIG_OFF ))
#define CDM_PSC1_MCLOCK		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_PSC1_MCLOCK_OFF))
#define CDM_PSC2_MCLOCK		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_PSC2_MCLOCK_OFF))
#define CDM_PSC3_MCLOCK		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_PSC3_MCLOCK_OFF))
#define CDM_PSC6_MCLOCK		((volatile UINT32 *)(CDM_BASE_ADRS + CDM_PSC6_MCLOCK_OFF))

/*-----------------------------------------------------------*/
/* LPC 												  0x0300 */
/*-----------------------------------------------------------*/

/* MBAR to LPC */
#define MBAR_LPC				0x0300

#define LPC_CS0_BOOT_CFG_OFF	0x0000
#define LPC_CS_CTRL_OFF			0x0018
#define LPC_CS_BURST_CTRL_OFF	0x0028
#define LPC_CS_DEAD_CTRL_OFF	0x002C

#define LPC_CS_CTRL_EBEE		0x8000
#define LPC_CS_CTRL_ME			0x0100

/*----------------------------------------------------------- */
/* Interrupt Controller (ICTL)                         0x0500 */
/*----------------------------------------------------------- */

#define MBAR_ICTL			0x0500

 
#define ICTL_PIMR_OFF		0x0		/* ICTL Peripheral Interrupt Mask Register */
#define ICTL_PPR_OFF		0x4		/* ICTL Peripheral Priority and HI/LO Select [3] Register */
#define ICTL_EEETR_OFF	    0x10	/* ICTL External Enable and Externals Types Register */
#define ICTL_CPMIMR_OFF	    0x14	/* ICTL Critical Priority and Main Interrupt Mask Register */
#define ICTL_MIPR_OFF		0x18	/* ICTL Main Interrupt Priority and INT/SMI Select [2] Register */
#define ICTL_ISR_OFF		0x24	/* ICTL PerStat, MainStat, CritStat Encoded Register */
#define ICTL_CISAR_OFF	    0x28	/* ICTL Critical Interrupt Status All Register */
#define ICTL_MISAR_OFF	    0x2C    /* ICTL Main Interrupt Status All Register */
#define ICTL_PISAR_OFF	    0x30    /* ICTL Peripheral Interrupt Status All Register */
#define ICTL_BISAR_OFF	    0x38    /* ICTL Bus Error Status Register */

#define ICTL_BASE_ADRS		(MBAR_VALUE + MBAR_ICTL)

#define ICTL_PIMR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_PIMR_OFF))
#define ICTL_PPR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_PPR_OFF))		/* [3] */
#define ICTL_EEETR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_EEETR_OFF))
#define ICTL_CPMIMR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_CPMIMR_OFF))
#define ICTL_MIPR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_MIPR_OFF))	/* [2] */
#define ICTL_ISR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_ISR_OFF))
#define ICTL_CISAR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_CISAR_OFF))
#define ICTL_MISAR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_MISAR_OFF))
#define ICTL_PISAR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_PISAR_OFF))
#define ICTL_BISAR			((volatile UINT32 *)(ICTL_BASE_ADRS + ICTL_BISAR_OFF))



/* External Enable and External Types Register */

#define ICTL_EEETR_ECLR0_MASK			(1<<27)
#define ICTL_EEETR_ECLR1_MASK			(1<<26)
#define ICTL_EEETR_ECLR2_MASK			(1<<25)
#define ICTL_EEETR_ECLR3_MASK			(1<<24)

#define ICTL_EEETR_ETYPE0_MASK			(3<<22)
#define ICTL_EEETR_ETYPE0_LEVEL_HI		(0<<22)
#define ICTL_EEETR_ETYPE0_RISING_EDGE	(1<<22)
#define ICTL_EEETR_ETYPE0_FALLING_EDGE	(2<<22)
#define ICTL_EEETR_ETYPE0_LEVEL_LO		(3<<22)

#define ICTL_EEETR_ETYPE1_MASK			(3<<20)
#define ICTL_EEETR_ETYPE1_LEVEL_HI		(0<<20)
#define ICTL_EEETR_ETYPE1_RISING_EDGE	(1<<20)
#define ICTL_EEETR_ETYPE1_FALLING_EDGE	(2<<20)
#define ICTL_EEETR_ETYPE1_LEVEL_LO 	 	(3<<20)

#define ICTL_EEETR_ETYPE2_MASK			(3<<18)
#define ICTL_EEETR_ETYPE2_LEVEL_HI		(0<<18)
#define ICTL_EEETR_ETYPE2_RISING_EDGE	(1<<18)
#define ICTL_EEETR_ETYPE2_FALLING_EDGE	(2<<18)
#define ICTL_EEETR_ETYPE2_LEVEL_LO		(3<<18)

#define ICTL_EEETR_ETYPE3_MASK			(3<<16)
#define ICTL_EEETR_ETYPE3_LEVEL_HI		(0<<16)
#define ICTL_EEETR_ETYPE3_RISING_EDGE	(1<<16)
#define ICTL_EEETR_ETYPE3_FALLING_EDGE	(2<<16)
#define ICTL_EEETR_ETYPE3_LEVEL_LO		(3<<16)


#define ICTL_EEETR_MEE					(1<<12)

#define ICTL_EEETR_EENA0_MASK			(1<<11)
#define ICTL_EEETR_EENA1_MASK			(1<<10)
#define ICTL_EEETR_EENA2_MASK			(1<<9)
#define ICTL_EEETR_EENA3_MASK			(1<<8)

#define ICTL_EEETR_CEb					(1<<0)

/* Critical Priority and Main Interrupt Mask Register */

#define ICTL_CPMIMR_MAIN_MASK0			(1<<16)
#define ICTL_CPMIMR_MAIN_MASK1			(1<<15)
#define ICTL_CPMIMR_MAIN_MASK2			(1<<14)
#define ICTL_CPMIMR_MAIN_MASK3			(1<<13)
#define ICTL_CPMIMR_MAIN_MASK4			(1<<12)
#define ICTL_CPMIMR_MAIN_MASK5			(1<<11)
#define ICTL_CPMIMR_MAIN_MASK6			(1<<10)
#define ICTL_CPMIMR_MAIN_MASK7			(1<<9)
#define ICTL_CPMIMR_MAIN_MASK8			(1<<8)
#define ICTL_CPMIMR_MAIN_MASK9			(1<<7)
#define ICTL_CPMIMR_MAIN_MASK10			(1<<6)
#define ICTL_CPMIMR_MAIN_MASK11			(1<<5)
#define ICTL_CPMIMR_MAIN_MASK12			(1<<4)
#define ICTL_CPMIMR_MAIN_MASK13			(1<<3)
#define ICTL_CPMIMR_MAIN_MASK14			(1<<2)
#define ICTL_CPMIMR_MAIN_MASK15			(1<<1)
#define ICTL_CPMIMR_MAIN_MASK16			(1<<0)
#define ICTL_CPMIMR_MASK_ALL			0x0001FFFF

/* Interrupt Status Register */

#define ICTL_CEbSh						(1<<0)
#define ICTL_ISR_CSe_SHIFT				8
#define ICTL_ISR_CSe_MASK				(7<<ICTL_ISR_CSe_SHIFT)
#define ICTL_ISR_CSe_MASK_NR			(3<<ICTL_ISR_CSe_SHIFT)
#define ICTL_ISR_MSe_SHIFT				16
#define ICTL_ISR_MSe_MASK				(0x3f<<ICTL_ISR_MSe_SHIFT)
#define ICTL_ISR_MSe_MASK_NR			(0x1f<<ICTL_ISR_MSe_SHIFT)
#define ICTL_ISR_PSe_SHIFT				24
#define ICTL_ISR_PSe_MASK				(0x3f<<ICTL_ISR_PSe_SHIFT)
#define ICTL_ISR_PSe_MASK_NR			(0x1f<<ICTL_ISR_PSe_SHIFT)

/*-----------------------------------------------------------*/
/* General Purpose Timer (GPT)                        0x0600 */
/*-----------------------------------------------------------*/

/* MBAR to GPT */
#define MBAR_GPT			0x0600	/* General Purpose Timer base register (GPT) */

#define GPT_NUM_TIMER_MAX	8	/* number of timers */

#define GPT_BASE(num)		((UINT32) (MBAR_VALUE + MBAR_GPT + (num*0x10)))

#define GPT_EMSR_OFF		0x0	/* GPT Enable and mode Select Register */
#define GPT_CIR_OFF			0x4	/* GPT Counter input register */
#define GPT_PWMCR_OFF		0x8	/* GPT PWM Configuration Register */
#define GPT_SR_OFF			0xc	/* GPT STatus Register */

#define GPT_EMSR(num)		((volatile UINT32 *) (GPT_BASE(num) + GPT_EMSR_OFF))
#define GPT_CIR(num)		((volatile UINT32 *) (GPT_BASE(num) + GPT_CIR_OFF))
#define GPT_PWMCR(num)		((volatile UINT32 *) (GPT_BASE(num) + GPT_PWMCR_OFF))
#define GPT_SR(num)			((volatile UINT32 *) (GPT_BASE(num) + GPT_SR_OFF))


/*-----------------------------------------------------------*/
/* Slice Timer (SLT)                                  0x0700 */
/*-----------------------------------------------------------*/

/* MBAR to SLT */
#define MBAR_SLT			0x0700	/* Slice Timer base register (SLT) */

#define SLT_NUM_TIMER_MAX	2	 /* number of timers */
#define SLT_ADRS_OFF		0x10 /* Timer 1 register offset from slt0 registers */


/* registers access definition */
#define SLT0_TCNT_OFF		0x00	/* SLT0 Terminal Count Register */
#define SLT0_CTRL_OFF		0x04	/* SLT0 Control Register */
#define SLT0_VALUE_OFF		0x08	/* SLT0 Count Value register */
#define SLT0_STATUS_OFF		0x0C	/* SLT0 Timer Status register */
	
#define SLT1_TCNT_OFF		0x10	/* SLT0 Terminal Count Register */
#define SLT1_CTRL_OFF		0x14	/* SLT0 Control Register */
#define SLT1_VALUE_OFF		0x18	/* SLT0 Count Value register */
#define SLT1_STATUS_OFF		0x1C	/* SLT0 Timer Status register */


	
#define SLT0_BASE_ADRS		(MBAR_VALUE + MBAR_SLT)
#define SLT_BASE(num)		((UINT32) (SLT0_BASE_ADRS + (num*0x10)))

#define SLT0_TCNT			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT0_TCNT_OFF))
#define SLT0_CTRL			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT0_CTRL_OFF))
#define SLT0_VALUE			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT0_VALUE_OFF))
#define SLT0_STATUS			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT0_STATUS_OFF))

#define SLT1_TCNT			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT1_TCNT_OFF))
#define SLT1_CTRL			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT1_CTRL_OFF))
#define SLT1_VALUE			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT1_VALUE_OFF))
#define SLT1_STATUS			((volatile UINT32 *) (SLT0_BASE_ADRS + SLT1_STATUS_OFF))

#define SLT_TCNT(num)		((volatile UINT32 *) (SLT_BASE(num) + SLT0_TCNT_OFF))
#define SLT_CTRL(num)		((volatile UINT32 *) (SLT_BASE(num) + SLT0_CTRL_OFF))
#define SLT_VALUE(num)		((volatile UINT32 *) (SLT_BASE(num) + SLT0_VALUE_OFF))
#define SLT_STATUS(num)	    ((volatile UINT32 *) (SLT_BASE(num) + SLT0_STATUS_OFF))


/* Control Register */
#define SLT_CTRL_ENABLE		0x01000000	/* Timer enable bit */
#define SLT_CTRL_INT_ENABLE	0x02000000	/* Interrupt enable bit */
#define SLT_CTRL_RUN_WAIT	0x04000000	/* Run/Wait bit (continusly mode or not) */

/* Status Register */
#define SLT_STATUS_RESET	0x01000000	/* ST bit - Timer reached terminal count */


/*-----------------------------------------------------------*/
/* Real Time Clock (RTC)							  0x0800 */
/*-----------------------------------------------------------*/

/* MBAR to GPT */
#define MBAR_RTC			0x0800	/* Real Time Clock base register */

#define RTC_BASE_ADRS		(MBAR_VALUE + MBAR_RTC)

#define RTC_TS_OFF			0x0	/* RTC Time Set Register */
#define RTC_DS_OFF			0x4	/* RTC Date Set register */
#define RTC_NYS_OFF			0x8	/* RTC New Year Software Register */
#define RTC_AIE_OFF			0xc	/* RTC Alarm/Interrupt Enable Register */

#define RTC_TS		((volatile UINT32 *) (RTC_BASE_ADRS + RTC_TS_OFF))
#define RTC_DS		((volatile UINT32 *) (RTC_BASE_ADRS + RTC_DS_OFF))
#define RTC_NYS		((volatile UINT32 *) (RTC_BASE_ADRS + RTC_NYS_OFF))
#define RTC_AIE		((volatile UINT32 *) (RTC_BASE_ADRS + RTC_AIE_OFF))


/*-----------------------------------------------------------*/
/* I 2 C controlers (I2C)                             0x3d00 */
/*-----------------------------------------------------------*/

/* MBAR to I2C */
#define MBAR_I2C			0x3d00	/* I2C base register (I2C) */

#define I2C_NUM_MAX			2		/* number of I2C controllers */
#define I2C_ADRS_OFF		0x40	/* I2C2 register offset from I2C1 */


/* registers access definition */
#define I2C_ADR_OFF			0x00	/* I2C Address Register */
#define I2C_FDR_OFF			0x04	/* I2C Frequency Divider Register */
#define I2C_CR_OFF			0x08	/* I2C Control register */
#define I2C_SR_OFF			0x0C	/* I2C Status register */
#define I2C_DIO_OFF			0x10	/* I2C data I/O register */
#define I2C_ICR_OFF			0x20	/* I2C Interrupt Control register */
	
#define I2C_BASE_ADRS		(MBAR_VALUE + MBAR_I2C)
#define I2C_BASE(num)		((UINT32) (I2C_BASE_ADRS + (num*I2C_ADRS_OFF)))

#define I2C_ADR(num)		((volatile UINT32 *) (I2C_BASE(num) + I2C_ADR_OFF))
#define I2C_FDR(num)		((volatile UINT32 *) (I2C_BASE(num) + I2C_FDR_OFF))