/* m5200FecEnd.h - Motorola MPC5200 Ethernet network interface header *//* Copyright 1990-2004 Wind River Systems, Inc. *//*modification history--------------------01g,17jul04,bjn  Correction to FEC_END_iaddr1_OFF & FEC_END_iaddr2_OFF01f,24jun04,bjn  Corrections to HASH registers01e,17jun04,bjn  RFIFO_ERROR - changes to fecStop/fecStart.01d,25may04,bjn  resolve various issues, see change log details (SPR97198)01c,15mar04,bjn  Support for Bestcomm 2.001b,18Jul03,pkr  adopted from motFecEnd01a,09nov98,cn   written.*//*change log details------------------01f * FEC_END_HASH_H_OFF and FEC_END_HASH_L_OFF offsets changed to      use GADDRs rather than IADDRs.01e * Added stoppingTx for handling of RFIFO_ERROR/XFIFO_ERROR01d * Increase FEC_END_BD_LOAN_NUM from 32 to 64. This creates more      network cluster buffers for the system to use and is necessary      to allow ping buffer sizes of 65500 bytes to be returned.      This results in m5200FecInitMem() allocating much more memory,      so this parameter is best trimmed to suit the application.    * Added BUF_TYPE_LOCAL, txBuffAvailable and pTxBuffLocal, requied      to ensure that TX packets get sent to the wire when NET_BUF_ALLOC()      returns NULL.*/#ifndef __INCm5200FecEndh#define __INCm5200FecEndh/* includes */#ifdef __cplusplusextern "C" {#endif/* defines *//* revision D.3 and greater processors require special FEC initialization */#define REV_D_4 0x0502#define REV_D_3 0x0501/* * redefine the macro below in the bsp if you need to access the device * registers/descriptors in a more suitable way. */#ifndef FEC_END_LONG_WR#define FEC_END_LONG_WR(addr, value)                                        \    (* (addr) = ((UINT32) (value)))#endif /* FEC_END_LONG_WR */#ifndef FEC_END_WORD_WR#define FEC_END_WORD_WR(addr, value)                                        \    (* (addr) = ((UINT16) (value)))#endif /* FEC_END_WORD_WR */#ifndef FEC_END_BYTE_WR#define FEC_END_BYTE_WR(addr, value)                                        \    (* (addr) = ((UINT8) (value)))#endif /* FEC_END_BYTE_WR */#ifndef FEC_END_LONG_RD#define FEC_END_LONG_RD(addr, value)                                        \    ((value) = (* (UINT32 *) (addr)))#endif /* FEC_END_LONG_RD */#ifndef FEC_END_WORD_RD#define FEC_END_WORD_RD(addr, value)                                        \    ((value) = (* (UINT16 *) (addr)))#endif /* FEC_END_WORD_RD */#ifndef FEC_END_BYTE_RD#define FEC_END_BYTE_RD(addr, value)                                        \    ((value) = (* (UINT8 *) (addr)))#endif /* FEC_END_BYTE_RD *//* * Default macro definitions for BSP interface. * These macros can be redefined in a wrapper file, to generate * a new module with an optimized interface. */#ifndef SYS_FEC_INT_CONNECT#define SYS_FEC_INT_CONNECT(pDrvCtrl, pFuncFEC, pFuncRDMA, pFuncWDMA, arg, ret) 	\{                                                                           		\IMPORT STATUS intConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int);		    				\ret = OK;                                                                   		\                                                                            		\if (!pDrvCtrl->intrConnect) 		    											\    {                                                                       		\	if (FEC_END_FEC_VECTOR (pDrvCtrl))				  		    					\    	{                                                                       	\    	ret = (intConnect) ((VOIDFUNCPTR*)                              	    	\        	                        INUM_TO_IVEC (FEC_END_FEC_VECTOR (pDrvCtrl)),  	\            	                    (pFuncFEC), (int) (arg));                     	\    	}                                                                       	\	if (FEC_END_RDMA_VECTOR (pDrvCtrl))				  		    					\    	{                                                                       	\    	ret = (intConnect) ((VOIDFUNCPTR*)                              	    	\        	                        INUM_TO_IVEC (FEC_END_RDMA_VECTOR (pDrvCtrl)),  \            	                    (pFuncRDMA), (int) (arg));                     	\    	}                                                                       	\ 	if (FEC_END_WDMA_VECTOR (pDrvCtrl))				  		    					\    	{                                                                       	\    	ret = (intConnect) ((VOIDFUNCPTR*)                              	    	\        	                        INUM_TO_IVEC (FEC_END_WDMA_VECTOR (pDrvCtrl)),  \            	                    (pFuncWDMA), (int) (arg));                     	\    	}                                                                       	\    pDrvCtrl->intrConnect = TRUE;                                   	    		\    }																				\}#endif /* SYS_FEC_INT_CONNECT */#ifndef SYS_FEC_INT_DISCONNECT#define SYS_FEC_INT_DISCONNECT(pDrvCtrl, pFuncFEC, pFuncRDMA, pFuncWDMA, arg, ret)	\{                                                                           		\ret = OK;                                                                   		\                                                                            		\if (m5200FecIntDisc != NULL)         							    	    		\    {                                                                       		\	if (FEC_END_FEC_VECTOR (pDrvCtrl))             	    							\    	{                                                                       	\    	ret = (*m5200FecIntDisc) ((VOIDFUNCPTR*)                          	    	\        	                      INUM_TO_IVEC (FEC_END_FEC_VECTOR (pDrvCtrl)),     \            	                  (pFuncFEC));                                     	\    	}																			\	if (FEC_END_RDMA_VECTOR (pDrvCtrl))             	    						\    	{                                                                       	\    	ret = (*m5200FecIntDisc) ((VOIDFUNCPTR*)                          	    	\        	                      INUM_TO_IVEC (FEC_END_RDMA_VECTOR (pDrvCtrl)),    \            	                  (pFuncRDMA));                                     \    	}																			\	if (FEC_END_WDMA_VECTOR (pDrvCtrl))             	    						\    	{                                                                       	\     	ret = (*m5200FecIntDisc) ((VOIDFUNCPTR*)                          	    	\        	                      INUM_TO_IVEC (FEC_END_WDMA_VECTOR (pDrvCtrl)),    \            	                  (pFuncWDMA));                                     \    	}																			\   	pDrvCtrl->intrConnect = FALSE;                                          		\    }																				\}#endif /* SYS_FEC_INT_DISCONNECT */#ifndef SYS_FEC_INT_ENABLE#define SYS_FEC_INT_ENABLE(pDrvCtrl, ret)				   		\{                                                               \IMPORT int intEnable (int);						    			\ret = OK;                                                       \                                                                \if (FEC_END_FEC_VECTOR (pDrvCtrl)) 			    			    \    ret = intEnable ((int) (FEC_END_FEC_VECTOR (pDrvCtrl)));	\if (FEC_END_RDMA_VECTOR (pDrvCtrl)) 			    			\    ret = intEnable ((int) (FEC_END_RDMA_VECTOR (pDrvCtrl)));	\if (FEC_END_WDMA_VECTOR (pDrvCtrl)) 			    			\    ret = intEnable ((int) (FEC_END_WDMA_VECTOR (pDrvCtrl)));	\}#endif /* SYS_FEC_INT_ENABLE */#ifndef SYS_FEC_INT_DISABLE#define SYS_FEC_INT_DISABLE(pDrvCtrl, ret)					    \{                                                               \IMPORT int intDisable (int);								    \ret = OK;                                                       \                                                                \if (FEC_END_FEC_VECTOR (pDrvCtrl)) 			    				\    ret = intDisable ((int) (FEC_END_FEC_VECTOR (pDrvCtrl)));	\if (FEC_END_RDMA_VECTOR (pDrvCtrl)) 			    			\    ret = intDisable ((int) (FEC_END_RDMA_VECTOR (pDrvCtrl)));	\if (FEC_END_WDMA_VECTOR (pDrvCtrl)) 			    			\    ret = intDisable ((int) (FEC_END_WDMA_VECTOR (pDrvCtrl)));	\}#endif /* SYS_FEC_INT_DISABLE */#define SYS_FEC_ENET_ADDR_GET(address)                                  \if (sysEnetAddrGet != NULL)                                          \    if (sysEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR)         \        {                                                               \        errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);                   \        return (NULL);                                                  \        }#define SYS_FEC_ENET_ENABLE                                             \if (sysFecEnetEnable != NULL)                                           \    if (sysFecEnetEnable (pDrvCtrl->fecBaseAddr) == ERROR)               \        return (ERROR);#define SYS_FEC_ENET_DISABLE                                            \if (sysFecEnetDisable != NULL)                                          \    if (sysFecEnetDisable (pDrvCtrl->fecBaseAddr) == ERROR)              \        return (ERROR);#define FEC_END_DEV_NAME       	"fec"#define FEC_END_DEV_NAME_LEN   	4#define FEC_END_TBD_DEF_NUM    	64		/* default number of TBDs */#define FEC_END_RBD_DEF_NUM    	48		/* default number of RBDs */#define FEC_END_TX_CL_NUM    	6		/* number of tx clusters */#define FEC_END_BD_LOAN_NUM    	64		/* loaned BDs */#define FEC_END_TBD_MAX         128     	/* max number of TBDs */#define FEC_END_RBD_MAX         128     	/* max number of TBDs */#define FEC_END_WAIT_MAX	0xf0000000	/* max delay after sending */#define FEC_END_ADDR_LEN        6               /* ethernet address length *//* Control/Status Registers (CSR) definitions */#define FEC_END_EVENT_OFF       0x0004  /* interrupt event register */#define FEC_END_MASK_OFF        0x0008  /* interrupt mask register */#define FEC_END_iaddr1_OFF      0x118#define FEC_END_iaddr2_OFF      0x11C#define FEC_END_CTRL_OFF        0x0024  /* FEC control register */#define FEC_END_MII_DATA_OFF    0x0040  /* MII data register */#define FEC_END_MII_SPEED_OFF   0x0044  /* MII speed register */#define FEC_END_RX_CTRL_OFF     0x0084  /* rx control register */#define FEC_END_TX_CTRL_OFF     0x00c4  /* tx control register */#define FEC_END_ADDR_L_OFF      0x00e4  /* lower 32-bits of MAC address */#define FEC_END_ADDR_H_OFF      0x00e8  /* upper 16-bits of MAC address */#define FEC_END_OP_PAUSE_OFF    0x00EC#define FEC_END_HASH_H_OFF      0x0120  /* upper 32-bits of hash table */#define FEC_END_HASH_L_OFF      0x0124  /* lower 32-bits of hash table */#define FEC_END_fifo_id_OFF     	0x140#define FEC_END_x_wmrk_OFF      	0x144#define FEC_END_fcntrl_OFF      	0x148#define FEC_END_r_bound_OFF     	0x14C#define FEC_END_r_fstart_OFF    	0x150#define FEC_END_r_count_OFF     	0x154#define FEC_END_r_lag_OFF       	0x158#define FEC_END_r_read_OFF      	0x15C#define FEC_END_r_write_OFF     	0x160#define FEC_END_x_count_OFF     	0x164#define FEC_END_x_lag_OFF       	0x168#define FEC_END_x_retry_OFF     	0x16C#define FEC_END_x_write_OFF     	0x170#define FEC_END_x_read_OFF      	0x174#define FEC_END_fm_cntrl_OFF    	0x180#define FEC_END_rfifo_data_OFF		0x184#define FEC_END_rfifo_status_OFF	0x188#define FEC_END_rfifo_cntrl_OFF		0x18C#define FEC_END_rfifo_lrf_ptr_OFF	0x190#define FEC_END_rfifo_lwf_ptr_OFF	0x194#define FEC_END_rfifo_alarm_OFF		0x198#define FEC_END_rfifo_rdptr_OFF		0x19C#define FEC_END_rfifo_wrptr_OFF		0x1A0#define FEC_END_tfifo_data_OFF		0x1A4#define FEC_END_tfifo_status_OFF	0x1A8#define FEC_END_tfifo_cntrl_OFF		0x1AC#define FEC_END_tfifo_lrf_ptr_OFF	0x1B0#define FEC_END_tfifo_lwf_ptr_OFF	0x1B4#define FEC_END_tfifo_alarm_OFF		0x1B8#define FEC_END_tfifo_rdptr_OFF		0x1BC#define FEC_END_tfifo_wrptr_OFF		0x1C0#define FEC_END_reset_cntrl_OFF		0x1C4#define FEC_END_xmit_fsm_OFF		0x1C8#define FEC_FIFO_STAT_ERROR			0x400000#define FEC_FIFO_STAT_UF			0x200000