#define MII_STAT_REG		0x1	/* Status Register */#define MII_PHY_ID1_REG		0x2	/* PHY identifier 1 Register */#define MII_PHY_ID2_REG		0x3	/* PHY identifier 2 Register */#define MII_AN_ADS_REG		0x4	/* Auto-Negotiation 	  */					/* Advertisement Register */#define MII_AN_PRTN_REG		0x5	/* Auto-Negotiation 	    */					/* partner ability Register */#define MII_AN_EXP_REG		0x6	/* Auto-Negotiation   */					/* Expansion Register */#define MII_AN_NEXT_REG		0x7	/* Auto-Negotiation 	       */					/* next-page transmit Register *//* MII control register bit  */#define MII_CR_COLL_TEST	0x0080		/* collision test */#define MII_CR_FDX		0x0100		/* FDX =1, half duplex =0 */#define MII_CR_RESTART		0x0200		/* restart auto negotiation */#define MII_CR_ISOLATE		0x0400		/* isolate PHY from MII */#define MII_CR_POWER_DOWN	0x0800		/* power down */#define MII_CR_AUTO_EN		0x1000		/* auto-negotiation enable */#define MII_CR_100		0x2000		/* 0 = 10mb, 1 = 100mb */#define MII_CR_LOOPBACK		0x4000		/* 0 = normal, 1 = loopback */#define MII_CR_RESET		0x8000		/* 0 = normal, 1 = PHY reset */#define MII_CR_NORM_EN		0x0000		/* just enable the PHY *//* MII Status register bit definitions */#define MII_SR_LINK_STATUS	0x0004       	/* link Status -- 1 = link */#define MII_SR_AUTO_SEL		0x0008       	/* auto speed select capable */#define MII_SR_REMOTE_FAULT     0x0010      	/* Remote fault detect */#define MII_SR_AUTO_NEG         0x0020      	/* auto negotiation complete */#define MII_SR_10T_HALF_DPX     0x0800     	/* 10BaseT HD capable */#define MII_SR_10T_FULL_DPX     0x1000    	/* 10BaseT FD capable */#define MII_SR_TX_HALF_DPX      0x2000    	/* TX HD capable */#define MII_SR_TX_FULL_DPX      0x4000     	/* TX FD capable */#define MII_SR_T4               0x8000    	/* T4 capable *//* MII Link Code word  bit definitions */#define MII_BP_FAULT	0x2000       	/* remote fault */#define MII_BP_ACK	0x4000       	/* acknowledge */#define MII_BP_NP	0x8000       	/* nexp page is supported *//* MII Next Page bit definitions */#define MII_NP_TOGGLE	0x0800       	/* toggle bit */#define MII_NP_ACK2	0x1000       	/* acknowledge two */#define MII_NP_MSG	0x2000       	/* message page */#define MII_NP_ACK1	0x4000       	/* acknowledge one */#define MII_NP_NP	0x8000       	/* nexp page will follow *//* MII Expansion Register bit definitions */#define MII_EXP_FAULT	0x0010       	/* parallel detection fault */#define MII_EXP_PRTN_NP	0x0008       	/* link partner next-page able */#define MII_EXP_LOC_NP	0x0004       	/* local PHY next-page able */#define MII_EXP_PR	0x0002       	/* full page received */#define MII_EXP_PRT_AN	0x0001       	/* link partner auto negotiation able *//* technology ability field bit definitions */#define MII_TECH_10BASE_T	0x0020	/* 10Base-T */#define MII_TECH_10BASE_FD	0x0040	/* 10Base-T Full Duplex */#define MII_TECH_100BASE_TX	0x0080	/* 100Base-TX */#define MII_TECH_100BASE_TX_FD	0x0100	/* 100Base-TX Full Duplex */#define MII_TECH_100BASE_T4	0x0200	/* 100Base-T4 */#define MII_TECH_MASK		0x1fe0	/* technology abilities mask */#define MII_AN_FAIL		0x10	/* auto-negotiation fail */#define MII_STAT_FAIL		0x20	/* errors in the status register */#define FEC_END_PHY_NO_ABLE	0x40	/* the PHY lacks some abilities *//* FEC_Lite FIFO Transmit Watermark Register(X_WMRK) definitions */#define FEC_XFIFO_WMRK_64        0x00000000  /* Transmit FIFO watermark(64 bytes) */#define FEC_XFIFO_WMRK_128       0x00000001  /* Transmit FIFO watermark(128 bytes) */#define FEC_XFIFO_WMRK_192       0x00000002  /* Transmit FIFO watermark(192 bytes) */#define FEC_XFIFO_WMRK_256       0x00000003  /* Transmit FIFO watermark(256 bytes) *//* FEC_Lite Opcode/Pause Duration Register(OP_PAUSE) definitions */#define FEC_OP_PAUSE_OPCODE      0x00010000  /* Opcode field used in PAUSE frames *//* settings *//* FEC-Lite RFIFO Control Register (RFIFO_CNTRL) definitions */#define FEC_RFIFO_CNTRL_FRAME    0x08000000  /* Frame mode enable */#ifdef BESTCOMM_API#define FEC_RFIFO_CNTRL_GR       0x07000000  /* Default Granularity value = 7 */#else#define FEC_RFIFO_CNTRL_GR       0x04000000  /* Default Granularity value = 4 */#endif/* FEC-Lite RFIFO Alarm Register (RFIFO_ALARM) definitions */#define FEC_RFIFO_ALARM          0x0000030C  /* Default value is 520 bytes *//* FEC-Lite XFIFO Control Register(XFIFO_CNTRL) definitions */#define FEC_XFIFO_CNTRL_FRAME    0x08000000  /* Frame mode enable */#ifdef BESTCOMM_API#define FEC_XFIFO_CNTRL_GR       0x07000000  /* Default Granularity value = 7 */#else#define FEC_XFIFO_CNTRL_GR       0x04000000  /* Default Granularity value = 4 */#endif#define FEC_PAUSE_DURATION       0x0020  /* Pause transmission for the duration *//* * this table may be customized by the user in configNet.h */IMPORT INT16 m5200FecPhyAnOrderTbl [];/* * the table below is used to translate user settings * into MII-standard values for technology abilities. */LOCAL UINT16 miiAnLookupTbl [] = {				  MII_TECH_10BASE_T,					  MII_TECH_10BASE_FD,				  MII_TECH_100BASE_TX,				  MII_TECH_100BASE_TX_FD,				  MII_TECH_100BASE_T4				         };LOCAL UINT16 miiCrLookupTbl [] = {				  MII_CR_NORM_EN,					  MII_CR_FDX,				  MII_CR_100,				  (MII_CR_100 | MII_CR_FDX),				  (MII_CR_100 | MII_CR_FDX)				         };typedef struct mii_regs    {    UINT16		phyStatus;	/* PHY's status register */    UINT16		phyCtrl;	/* PHY's control register */    UINT16		phyId1;		/* PHY's identifier field 1 */    UINT16		phyId2;		/* PHY's identifier field 2 */    UINT16		phyAds;		/* PHY's advertisement register */    UINT16		phyPrtn;	/* PHY's partner register */    UINT16		phyExp;		/* PHY's expansion register */    UINT16		phyNext;	/* PHY's next paget transmit register */    } MII_REGS;typedef struct phy_info    {    MII_REGS		miiRegs;	/* PHY registers */    UINT8		phyAddr;	/* address of the PHY to be used */    UINT8		isoPhyAddr;	/* address of a PHY to isolate */    UINT32		phyFlags;	/* some flags */    UINT32              phySpeed;     	/* 10/100 Mbit/sec */    UINT32              phyMode;     	/* half/full duplex mode */    UINT32              phyDefMode;    	/* default operating mode */    } PHY_INFO;typedef struct mot_fec_tbd_list    {    UINT16			fragNum;    UINT16			pktType;    UCHAR *			pBuf;    UINT16			bufType;    struct mot_fec_tbd_list *	pNext;    FEC_END_TBD_ID		pTbd;    } FEC_END_TBD_LIST;typedef FEC_END_TBD_LIST *	FEC_END_TBD_LIST_ID;/* The definition of the driver control structure */typedef struct drv_ctrl    {    END_OBJ             endObj;         /* base class */    int                 unit;           /* unit number */    UINT32              fecBaseAddr;    /* internal RAM base address */    VOIDFUNCPTR *       ivecFEC;        /* interrupt vector number FEC */    VOIDFUNCPTR *       ivecRDMA;       /* interrupt vector number RDMA */    VOIDFUNCPTR *       ivecWDMA;       /* interrupt vector number WDMA */    UINT32              fifoTxBase;     /* address of Tx FIFO in internal RAM */    UINT32              fifoRxBase;     /* address of Rx FIFO in internal RAM */    char *              pBufBase;       /* FEC memory pool base */    ULONG               bufSize;        /* FEC memory pool size */    UINT16              rbdNum;         /* number of RBDs */ #ifndef BESTCOMM_API    FEC_END_RBD_ID	    rbdBase;        /* RBD ring */ #else    int					recvTaskNo;		/* Bestcomm Task for Receive */    int			rxPollTID; #endif    UINT16              rbdIndex;       /* RBD index */    UINT16              tbdNum;         /* number of TBDs */    FEC_END_TBD_ID	    tbdBase;        /* TBD ring */ #ifdef BESTCOMM_API    int					xmitTaskNo;		/* Bestcomm Task for Transmit */ #endif    UINT16              tbdIndex;       /* TBD index */    UINT16              usedTbdIndex;   /* used TBD index */    volatile UINT16     cleanTbdNum;    /* number of clean TBDs */    BOOL                txStall;        /* tx handler stalled - no Tbd */    FEC_END_TBD_LIST * 	pTbdList [FEC_END_TBD_MAX];					/* list of TBDs */    ULONG               userFlags;      /* some user flags */    INT8                flags;          /* driver state */    BOOL                loaded;         /* interface has been loaded */    BOOL                intrConnect;    /* interrupt has been connected */    UINT32				intMask;	/* interrupt mask register */    UCHAR *				pTxPollBuf;	/* cluster pointer for poll mode */    UCHAR *            	rxBuf[FEC_END_RBD_MAX];                                        /* array of pointers to clusters */    SEM_ID				miiSem;		/* synch semaphore for mii frames */    SEM_ID				graSem;		/* synch semaphore for graceful */					/* transmit command */    char *              pClBlkArea;     /* cluster block pointer */    UINT32              clBlkSize;     	/* clusters block memory size */    char *              pMBlkArea;     	/* mBlock area pointer */    UINT32              mBlkSize;     	/* mBlocks area memory size */    CACHE_FUNCS         bdCacheFuncs;   /* cache descriptor */    CACHE_FUNCS         bufCacheFuncs;  /* cache descriptor */    CL_POOL_ID          pClPoolId;      /* cluster pool identifier */    PHY_INFO		*phyInfo;	/* info on a MII-compliant PHY */    UINT32		clockSpeed;	/* clock speed (Hz) for MII_SPEED */    UINT8               txBuffAvailable; /* Flag for use with pTxBuffLocal */    char *              pTxBuffLocal;    /* Local buffer for sending data */    UINT32              stoppingTx; /* Flag to stop sending frames after */                                    /* fecStop has been scheduled */    } DRV_CTRL;/* * this cache functions descriptors is used to flush/invalidate * the FEC's data buffers. They are set to the system's cache * flush and invalidate routine. This will allow proper operation * of the driver if data cache are turned on. */IMPORT STATUS   cacheArchInvalidate (CACHE_TYPE, void *, size_t);IMPORT STATUS   cacheArchFlush (CACHE_TYPE, void *, size_t);LOCAL   CACHE_FUNCS     m5200FecBufCacheFuncs;LOCAL	FUNCPTR m5200FecBufInvRtn = cacheArchInvalidate;LOCAL	FUNCPTR m5200FecBufFlushRtn = cacheArchFlush;LOCAL   FUNCPTR m5200FecIntDisc = NULL;   /* assign a proper disc routine */IMPORT STATUS	sysEnetAddrGet (UINT32 motCmpAddr, UCHAR * address);IMPORT STATUS	sysEnetAddrSet (UINT32 motCmpAddr, UCHAR * address);IMPORT STATUS	sysFecEnetEnable (UINT32 motCmpAddr);IMPORT STATUS	sysFecEnetDisable (UINT32 motCmpAddr);IMPORT FUNCPTR  _func_m5200FecPhyInit;IMPORT FUNCPTR  _func_m5200FecHbFail;#ifdef __cplusplus}#endif#endif /* __INCm5200FecEndh */