#define SPECIFIED_INTR_REG                    21                /* PHY Specified Interrupt Reg */


/*
*********************************************************************************************************
*                                               DEFINES
*********************************************************************************************************
*/

#define  EMAC_MAN_WRITE             (0x01 << 28)                        /* 01: Transfer is a write.                             */
#define  EMAC_MAN_READ              (0x02 << 28)                        /* 10: Transfer is a read.                              */
#define  EMAC_MAN_CODE              (0x02 << 16)                        /* IEEE Code. MUST have value of 10.                    */

#define  EMAC_RXBUF_ADDRESS_MASK    (0xFFFFFFFC)                        /* Addr of Rx Descriptor Buf's (wrap/ownership ignored  */
#define  EMAC_RXBUF_ADD_WRAP        (0x01 <<  1)                        /* This is the last buffer in the ring.                 */
#define  EMAC_RXBUF_SW_OWNED        (0x01 <<  0)                        /* Software owns the buffer.                            */
#define  EMAC_RXBUF_LEN_MASK        (0x00000FFF)                        /* Length of frame including FCS. (12 bits)             */
#define  EMAC_RXBUF_SOF_MASK        (0x01 << 14)                        /* Start of frame mask                                  */
#define  EMAC_RXBUF_EOF_MASK        (0x01 << 15)                        /* End of frame mask                                    */
#define  EMAC_RXBUF_OFF_MASK        (0x03 << 12)                        /* Data offset mask (up to three bytes possible)        */

#define  EMAC_TXBUF_ADD_WRAP        (0x01 << 30)                        /* This is the last buffer in the ring.                 */
#define  EMAC_TXBUF_TX_SIZE_MASK    (0x000007FF)                        /* Length of frame including FCS. (11 bits)             */
#define  EMAC_TXBUF_ADD_LAST        (0x01 << 15)                        /* This is the last buffer for the current frame        */

#define  EMAC_TXBUF_STATUS_USED     (CPU_INT32U)(0x01 << 31)            /* Status Used Bit. Indicates when a buf has been read  */

/*
*********************************************************************************************************
*                                               MACROS
*********************************************************************************************************
*/

#define  EMAC_MAN_REGA(_x_)         (_x_         << 18)                 /* Specifies the register in the PHY to access.         */
#define  EMAC_MAN_PHYA(_x_)        ((_x_ & 0x1F) << 23)                 /* PHY address. Normally 0.                             */
#define  EMAC_MAN_DATA(_x_)         (_x_ & 0xFFFF)                      /* PHY Read/Write Data Mask. */

/*
*********************************************************************************************************
*                                     PHYSICAL LAYER DEFINITIONS
*********************************************************************************************************
*/
#define  BSP_XTAL_FREQ 18432L   /* onboard crystal frequency (khz) */

#define  NET_PHY_SPD_0                                     0    /* Link speed unknown, or link down                     */
#define  NET_PHY_SPD_10                                   10    /* Link speed = 10mbps                                  */
#define  NET_PHY_SPD_100                                 100    /* Link speed = 100mbps                                 */
#define  NET_PHY_SPD_1000                               1000    /* Link speed = 1000mbps                                */

#define  NET_PHY_DUPLEX_UNKNOWN                            0    /* Duplex uknown or auto-neg incomplete                 */
#define  NET_PHY_DUPLEX_HALF                               1    /* Duplex = Half Duplex                                 */
#define  NET_PHY_DUPLEX_FULL                               2    /* Duplex = Full Duplex                                 */
/* 接收緩沖區描述符標志位及狀態位宏定義 */
#define		RxDESC_FLAG_WARP			0x00000002				//* 標記接收緩沖區描述符列表中的最后一個描述符
#define		RxDESC_FLAG_OWNSHIP			0x00000001				//* 標記接收緩沖區為程序所有

/* 發送緩沖區描述狀態信息宏定義 */
#define 	TxDESC_STATUS_BUF_SIZE		((ULONG)0x000007FF)		//* 緩沖區長度
#define 	TxDESC_STATUS_LAST_BUF		((ULONG)(1 << 15))		//* 幀的最后一個緩沖區
#define		TxDESC_STATUS_NO_CRC		((ULONG)(1 << 16))		//* 沒有CRC被附加到當前幀	
#define		TxDESC_STATUS_BUF_EXHAUSTED	((ULONG)(1 << 27))		//* 發送中途緩沖區就被用光
#define		TxDESC_STATUS_Tx_UNDERRUN	((ULONG)(1 << 28))		//* 發送欠速
#define		TxDESC_STATUS_Tx_ERROR		((ULONG)(1 << 29))		//* 發送錯誤
#define		TxDESC_STATUS_WRAP			((ULONG)(1 << 30))		//* 最后一個緩沖區
#define		TxDESC_STATUS_USED			((ULONG)(1 << 31))		//* 如果成功發送，緩沖區描述符隊列的第一個緩沖區描述符的USED狀態位被EMAC置位

//* 接收緩沖區描述符結構，參見AT91SAM7X256數據手冊（完整版）
#define		EMAC_RxB_ADDR_MASK			0xFFFFFFFC
typedef struct{
	ULONG ulRxBAddrAndFlag;
	union
	{
		ULONG ulStatus;
		struct {
			ULONG bitLen					:12;
			ULONG bitRxBOffset				:2;
			ULONG bitStartOfFrm				:1;
			ULONG bitEndOfFrm				:1;
			ULONG bitCFI					:1;
			ULONG bitVLANPrio				:3;
			ULONG bitPrioTag				:1;
			ULONG bitVLANTag				:1;
			ULONG bitTypeID					:1;
			ULONG bitSA4Match				:1;
			ULONG bitSA3Match				:1;
			ULONG bitSA2Match				:1;
			ULONG bitSA1Match				:1;
			ULONG bitRsrved0				:1;
			ULONG bitExtAddrMatch			:1;
			ULONG bitUniCastHashMatch		:1;
			ULONG bitMultiCastHashMatch		:1;
			ULONG bitIsBroadCastAddr		:1;
		}bstStatus;		
	}uStatus;
}AT91S_RxBDescriptor, *AT91PS_RxBDescriptor;

//* 發送緩沖區描述符結構，按照EMAC數據手冊的描述建立，參見AT91SAM7X256數據手冊（完整版）EMAC部分 
typedef struct{
	ULONG ulTxBAddr;
	union
	{
		ULONG ulStatus;
		struct {
			ULONG bitLen			:11;
			ULONG bitRsrved0		:4;
			ULONG bitIsLastBuf		:1;
			ULONG bitIsNoCRC		:1;
			ULONG bitRsrved1		:10;
			ULONG bitIsBExhausted	:1;
			ULONG bitIsTxUnderrun	:1;
			ULONG bitTxError		:1;
			ULONG bitIsWrap			:1;
			ULONG bitIsUsed			:1;
		}bstStatus;		
	}uStatus;
}AT91S_TxBDescriptor, *AT91PS_TxBDescriptor;										
										
										
//* 使能EMAC管理數據接口
#define		EnableMDI()										\
{															\
	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;			\
}

//* 禁止EMAC管理數據接口
#define		DisableMDI()							\
{													\
	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	\
}										
//*-----------------------------------------函數原型生命--------------------------------------------
extern void EMACInit(NET_ERR  *perr);
//*-------------------------------------------------------------------------------------------------
#endif