/****************************************Copyright (c)**************************************************
**                               Guangzou ZLG-MCU Development Co.,LTD.
**                                      graduate school
**                                 http://www.zlgmcu.com
**
**--------------File Info-------------------------------------------------------------------------------
** File Name: dm9000_driver.h
** Last modified Date:  2004-11-27
** Last Version: 1.0
** Descriptions: dm9000_driver HEAD FILE
**
**------------------------------------------------------------------------------------------------------
** Created By: Yehaoben
** Created date:   2004-11-27
** Version: 1.0
** Descriptions: First version
**
**------------------------------------------------------------------------------------------------------
** Modified by:
** Modified date:
** Version:
** Descriptions:
**
********************************************************************************************************/

/********************************************************************************************************
**                             Configration Setting
********************************************************************************************************/
#define IOaddress0		0x83000000
#define IOaddress1		0x82000310	//default value
#define IOaddress2		0x82000320	//default value

#define NET_RST0   		0X00000100//0X00000400
#define NET_RST1 
#define NET_RST2 

#define	BUS_DELAY		200

#define	Hardware_Initial0()	{IODIR=IODIR|NET_RST0;}
#define	Hardware_Reset_Clr0()	{IOCLR=NET_RST0;}
#define	Hardware_Reset_Set0()	{IOSET=NET_RST0;}

#define	Hardware_Initial1()	
#define	Hardware_Reset_Clr1()	
#define	Hardware_Reset_Set1()	

#define	Hardware_Initial2()	
#define	Hardware_Reset_Clr2()	
#define	Hardware_Reset_Set2()	

#define DM9000_REG00		0x00
#define DM9000_REG05		0x0A		/*DISCARD LONG\CRC_ERR\mutilcast\Promiscuous,Pass Runt,RX not enable *///0x30	/* SKIP_CRC/SKIP_LONG */
#define DM9000_REG08		0x37
#define DM9000_REG09		0x38
#define DM9000_REG0A		0xff 
#define DM9000_REGFF		0x83	/* IMR return auto;TX lunch;RX lunch*/

/********************************************************************************************************
**                            Define
********************************************************************************************************/

#define DM9000_DWORD_MODE	1
#define DM9000_BYTE_MODE	2
#define DM9000_WORD_MODE	0

#define DM9801_NOISE_FLOOR	0x08
#define DM9802_NOISE_FLOOR	0x05

#define DM9000_PHY		0x40	/* PHY address 0x01 */
#define DM9000_PKT_MAX		1536	/* Received packet max size */
#define DM9000_PKT_RDY		0x01	/* Packet ready to receive */
#define DM9000_MIN_IO		0x300
#define DM9000_MAX_IO		0x370
#define DM9000_INT_MII		0x00
#define DM9000_EXT_MII		0x80

#define DM9000_RX_INTR		0x01
#define DM9000_TX_INTR		0x02
#define DM9000_OVERFLOW_INTR	0x04

enum DM9000_PHY_mode {
	DM9000_10MHD   = 0, 
	DM9000_100MHD  = 1, 
	DM9000_10MFD   = 4,
	DM9000_100MFD  = 5, 
	DM9000_AUTO    = 8, 
	DM9000_1M_HPNA = 0x10 
};

enum DM9000_NIC_TYPE {
	FASTETHER_NIC = 0, 
	HOMERUN_NIC   = 1, 
	LONGRUN_NIC   = 2 
};
/********************************************************************************************************
**                             Structure Define
********************************************************************************************************/
/* Structure/enum declaration ------------------------------- */
typedef struct board_info {

	uint32 ioaddr;			/* Register I/O base address */
	uint32 io_data;			/* Data I/O address */
	uint16 irq;			/* IRQ */

	uint16 queue_pkt_len;
	uint8 reg0, reg5, reg8, reg9, rega;/* registers saved */
	uint8 op_mode;			/* PHY operation mode */
	uint8 io_mode;			/* 0:word, 2:byte */
	uint8 phy_addr;
	uint8 link_failed;			/* Ever link failed */
	uint8 nic_type;			/* NIC type */
	uint8 nic_mac[6];
} board_info_t;