/*---------------------------------------------------------------------*
   FILENAME:                     SERCpu.H

                  Some definitions used by SERIAL.C

 *--------------------------------------------------------------------*/

#define COM5            5
#define COM6            6
#define COM5BASE        0xff80   /*  Base port address for COM5  */
#define COM6BASE        0xff10   /*  Base port address for COM6  */

/*
    	o TXR Output data to the serial port.
	o RXR Input data from the serial port.
	o LCR Initialize the serial port.
	o IER Controls interrupt generation.
	o IIR Identifies interrupts.
	o MCR Send contorl signals to the modem.
	o LSR Monitor the status of the serial port.
	o MSR Receive status of the modem.
	o DLL Low byte of baud rate divisor.
	o DHH High byte of baud rate divisor.
*/
#define TXRCPU             0       /*  Transmit register (WRITE) */
#define RXRCPU             0       /*  Receive register  (READ)  */
#define IERCPU             2       /*  Interrupt Enable          */
#define IIRCPU             4       /*  Interrupt ID              */
#define LCRCPU             6       /*  Line control              */
#define MCRCPU             8       /*  Modem control             */
#define LSRCPU             0x0a       /*  Line Status               */
#define MSRCPU             0x0c       /*  Modem Status              */
#define DLLCPU             0       /*  Divisor Latch Low         */
#define DLHCPU             2       /*  Divisor latch High        */


/*-------------------------------------------------------------------*
  Bit values held in the Line Control Register (LCR).
	bit		meaning
	---		-------
	0-1		00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits.
	2		Stop bits.
	3		0=parity off, 1=parity on.
	4		0=parity odd, 1=parity even.
	5		Sticky parity.
	6		Set break.
	7		Toggle port addresses.
 *-------------------------------------------------------------------*/
#define NO_PARITY       0x00
#define EVEN_PARITY     0x18
#define ODD_PARITY      0x08



/*-------------------------------------------------------------------*
  Bit values held in the Line Status Register (LSR).
	bit		meaning
	---		-------
	0		Data ready.
	1		Overrun error - Data register overwritten.
	2		Parity error - bad transmission.
	3		Framing error - No stop bit was found.
	4		Break detect - End to transmission requested.
	5		Transmitter holding register is empty.
	6		Transmitter shift register is empty.
	7               Time out - off line.
 *-------------------------------------------------------------------*/
#define RCVRDY          0x01
#define OVRERR          0x02
#define PRTYERR         0x04
#define FRMERR          0x08
#define BRKERR          0x10
#define XMTRDY          0x20
#define XMTRSR          0x40
#define TIMEOUT		0x80

/*-------------------------------------------------------------------*
  Bit values held in the Modem Output Control Register (MCR).
	bit     	meaning
	---		-------
	0		Data Terminal Ready. Computer ready to go.
	1		Request To Send. Computer wants to send data.
	2		auxillary output #1.
	3		auxillary output #2.(Note: This bit must be
			set to allow the communications card to send
			interrupts to the system)
	4		UART ouput looped back as input.
	5-7		not used.
 *------------------------------------------------------------------*/
#define DTR             0x01
#define RTS             0x02
#define MC_INT		0x08


/*------------------------------------------------------------------*
  Bit values held in the Modem Input Status Register (MSR).
	bit		meaning
	---		-------
	0		delta Clear To Send.
	1		delta Data Set Ready.
	2		delta Ring Indicator.
	3		delta Data Carrier Detect.
	4		Clear To Send.
	5		Data Set Ready.
	6		Ring Indicator.
	7		Data Carrier Detect.
 *------------------------------------------------------------------*/
#define CTS             0x10
#define DSR             0x20


/*------------------------------------------------------------------*
  Bit values held in the Interrupt Enable Register (IER).
	bit		meaning
	---		-------
	0		Interrupt when data received.
	1		Interrupt when transmitter holding reg. empty.
	2		Interrupt when data reception error.
	3		Interrupt when change in modem status register.
	4-7		Not used.
 *------------------------------------------------------------------*/
#define RX_INT          0x01


/*------------------------------------------------------------------*
  Bit values held in the Interrupt Identification Register (IIR).
	bit		meaning
	---		-------
	0		Interrupt pending
	1-2             Interrupt ID code
			00=Change in modem status register,
			01=Transmitter holding register empty,
			10=Data received,
			11=reception error, or break encountered.
	3-7		Not used.
 *------------------------------------------------------------------*/
#define NO_INT		0x01
#define URS_ID		0x06
#define RX_ID           0x04
#define FDT_ID		0x0c
#define TBRE_ID		0x02
#define HSR_ID		0x0
#define RX_MASK         0x0f


/*
    These are the port addresses of the 8259 Programmable Interrupt
    Controller (PIC).
*/
#define IMRCPU             0xff28   /* Interrupt Mask Register port */
#define ICRCPU             0xff22   /* Interrupt Control Port       */


/*
    An end of interrupt needs to be sent to the Control Port of
    the 8259 when a hardware interrupt ends.
*/

#define EOICPU         0x8000    /* End Of Interrupt */

/*
    The (IMR) tells the (PIC) to service an interrupt only if it
    is not masked (FALSE).
*/
#define COM5MC           0xfbff /* COM5 */
#define COM6MC           0xfdff /* COM6 */
#define REG_SVER	 0xff2c /*中斷服務寄存器*/
#define CPU_CLOCK_RATE	 100    /*根據CPU頻率設定，如cpu頻率為100M則設為100*/
#define CPU_CLOCK_BASE   25
#define F11		(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*14204                            /*  110 baud clock divisor	*/
#define F150  		(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*10417                           /*  150 baud clock divisor      */
#define F300       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*5208				/*  300 baud clock divisor      */
#define F600       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*2604	                        /*  600 baud clock divisor      */
#define F1200       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*1302                            /* 1200 baud clock divisor      */
#define F2400       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*651                             /* 2400 baud clock divisor      */
#define F4800       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*326                             /* 4800 baud clock divisor      */
#define F9600       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163                             /* 9600 baud clock divisor      */
#define F19200       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/2                           /*  19200 baud clock divisor    */
#define F38400       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/4				/* 38400 baud clock divisor     */
#define F57600       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/6	                        /*  57600 baud clock divisor    */
#define F115200       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/12                          /* 115200 baud clock divisor    */
#define F230400       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/24                          /* 230400 baud clock divisor    */
#define F460800       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/48                          /* 460800 baud clock divisor    */
#define F921600       	(CPU_CLOCK_RATE/CPU_CLOCK_BASE)*163/96                         /* 921600 baud clock divisor    */
#define VID		1
/*恢復軟中斷入口參數*/
#define ENTRY_SOFT_INT(x)  \
			asm	mov	ax,seg x;\
			asm	mov	bx,offset x;\
			asm	mov	ds,ax;\
			asm	mov	ax,ds:[bx+2];\
			asm	mov	bx,ds:[bx];\
			asm	xchg	ax,ss:[bp+16];\
			asm	xchg    bx,ss:[bp+14];\
			asm     mov	sp,bp;\
			asm	pop	bp;\
			asm 	pop	di;\
			asm 	pop	si;\
			asm 	pop	ds;\
			asm 	pop	es;\
			asm 	pop	dx;\
			asm 	pop	cx;\
			asm	retf;