?? rt73.h
字號:
/*
***************************************************************************
* Ralink Tech Inc.
* 4F, No. 2 Technology 5th Rd.
* Science-based Industrial Park
* Hsin-chu, Taiwan, R.O.C.
*
* (c) Copyright 2002-2006, Ralink Technology, Inc.
*
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
************************************************************************
Module Name:
rt73.h
Abstract:
RT2573 ASIC related definition & structures
Revision History:
Who When What
-------- ---------- ----------------------------------------------
Nemo Tang 02-20-2005 created
*/
#ifndef __RT73_H__
#define __RT73_H__
////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////
// reg for RT73 ///////////
//////////////////////////
// 8051 firmware image - base address = 0x4000
#define FIRMWARE_IMAGE_BASE 0x800
#define MAX_FIRMWARE_IMAGE_SIZE 2048 // 2kbytes
//
// Security key table memory, base address = 0x1000
//
#define SHARED_KEY_TABLE_BASE 0x1000 // 32-byte * 16-entry = 512-byte
#define PAIRWISE_KEY_TABLE_BASE 0x1200 // 32-byte * 64-entry = 2048-byte
#define PAIRWISE_TA_TABLE_BASE 0x1a00 // 8-byte * 64-entry = 512-byte
// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
typedef struct _HW_KEY_ENTRY { // 32-byte per entry
UCHAR Key[16];
UCHAR TxMic[8];
UCHAR RxMic[8];
} HW_KEY_ENTRY, *PHW_KEY_ENTRY;
#define HW_KEY_ENTRY_SIZE sizeof(HW_KEY_ENTRY)
// 64-entry for pairwise key table
typedef struct _HW_PAIRWISE_TA_ENTRY { // 8-byte per entry
UCHAR Address[6];
UCHAR Rsv[2];
} HW_PAIRWISE_TA_ENTRY, PHW_PAIRWISE_TA_ENTRY;
#define HW_PAIRWISE_TA_ENTRY_SIZE sizeof(HW_PAIRWISE_TA_ENTRY)
#define HW_DEBUG_SETTING_BASE 0x2bf0 // 0x2bf0~0x2bff total 16 bytes
#define HW_DEBUG_SETTING_END 0x2bff
// on-chip BEACON frame space - base address = 0x2400
#define HW_BEACON_BASE0 0x2400
#define HW_BEACON_BASE1 0x2500
#define HW_BEACON_BASE2 0x2600
#define HW_BEACON_BASE3 0x2700
//
// MAC Control Registers - base address 0x3000
//
#define MAC_CSR0 0x3000
#define MAC_CSR1 0x3004
#define MAC_CSR2 0x3008
#define MAC_CSR3 0x300c
#define MAC_CSR4 0x3010
#define MAC_CSR5 0x3014
#define MAC_CSR6 0x3018
#define MAC_CSR7 0x301c
#define MAC_CSR8 0x3020 // SIFS/EIFS
#define MAC_CSR9 0x3024
#define MAC_CSR10 0x3028 // power state configuration
#define MAC_CSR11 0x302c // Power state transition time
#define MAC_CSR12 0x3030 // power state
#define MAC_CSR13 0x3034 // GPIO
#define MAC_CSR14 0x3038 // LED control
#define MAC_CSR15 0x303c // NAV control
//
// TXRX control registers - base address 0x3000
//
#define TXRX_CSR0 0x3040
#define TXRX_CSR1 0x3044
#define TXRX_CSR2 0x3048
#define TXRX_CSR3 0x304c
#define TXRX_CSR4 0x3050
#define TXRX_CSR5 0x3054
#define TXRX_CSR6 0x3058 // ACK/CTS payload consumed time
#define TXRX_CSR7 0x305c // ACK/CTS payload consumed time
#define TXRX_CSR8 0x3060 // ACK/CTS payload consumed time
#define TXRX_CSR9 0x3064 // BEACON SYNC
#define TXRX_CSR10 0x3068 // BEACON alignment
#define TXRX_CSR11 0x306c // AES mask
#define TXRX_CSR12 0x3070 // TSF low 32
#define TXRX_CSR13 0x3074 // TSF high 32
#define TXRX_CSR14 0x3078 // TBTT timer
#define TXRX_CSR15 0x307c // TKIP MIC priority byte "AND" mask
//
// PHY control registers - base address 0x3000
//
#define PHY_CSR0 0x3080 // RF/PS control
#define PHY_CSR1 0x3084
#define PHY_CSR2 0x3088 // pre-TX BBP control
#define PHY_CSR3 0x308c // BBP access
#define PHY_CSR4 0x3090 // RF serial control
#define PHY_CSR5 0x3094 // RX to TX signal switch timing control
#define PHY_CSR6 0x3098 // TX to RX signal timing control
#define PHY_CSR7 0x309c // TX DAC switching timing control
//
// Security control register - base address 0x3000
//
#define SEC_CSR0 0x30a0 // shared key table control
#define SEC_CSR1 0x30a4 // shared key table security mode
#define SEC_CSR2 0x30a8 // pairwise key table valid bitmap 0
#define SEC_CSR3 0x30ac // pairwise key table valid bitmap 1
#define SEC_CSR4 0x30b0 // pairwise key table lookup control
#define SEC_CSR5 0x30b4 // shared key table security mode
//
// STA control registers - base address 0x3000
//
#define STA_CSR0 0x30c0 // CRC/PLCP error counter
#define STA_CSR1 0x30c4 // Long/False-CCA error counter
#define STA_CSR2 0x30c8 // RX FIFO overflow counter
#define STA_CSR3 0x30cc // TX Beacon counter
#define STA_CSR4 0x30d0 // TX Retry (1) Counters
#define STA_CSR5 0x30d4 // TX Retry (2) Counters
//
// QOS control registers - base address 0x3000
//
#define QOS_CSR0 0x30e0 // TXOP holder MAC address 0
#define QOS_CSR1 0x30e4 // TXOP holder MAC address 1
#define QOS_CSR2 0x30e8 // TXOP holder timeout register
#define QOS_CSR3 0x30ec // RX QOS-CFPOLL MAC address 0
#define QOS_CSR4 0x30f0 // RX QOS-CFPOLL MAC address 1
#define QOS_CSR5 0x30f4 // "QosControl" field of the RX QOS-CFPOLL
////////WMM Scheduler Register////////////
#define AIFSN_CSR 0x0400
#define CWMIN_CSR 0x0404
#define CWMAX_CSR 0x0408
#define AC_TXOP_CSR0 0x040c
#define AC_TXOP_CSR1 0x0410
////////////////////////////////////////////////////////////////////////////////////////
// ================================================================
// Tx / Rx / Mgmt ring descriptor definition
// ================================================================
// value domain of pTxD->Owner and pRxD->Owner
#define DESC_OWN_HOST 0
#define DESC_OWN_NIC 1
// the following PID values are used to mark outgoing frame type in TXD so that
// proper TX statistics can be collected based on these categories
#define PID_DATA_REQUIRE_ACK 0x00 // b0~6 = MAC table index when acking as AP
#define PID_DATA_WITHOUT_ACK 0x40 // b0~6 = MAC table index when acting as AP
#define PID_NULL_AT_HIGH_RATE 0x80
#define PID_RTS_FRAME 0x81
#define PID_MGMT_FRAME 0x82
#define PID_CNTL_FRAME 0x83 // other non-RTS Control frame
#define PID_MCU_INTERNAL 0xff // frame generated internally by 8051
#if 0
// the following PID values are used to mark outgoing frame type in TXD->PID so that
// proper TX statistics can be collected based on these categories
// b7-6 of PID field -
#define PTYPE_DATA_REQUIRE_ACK 0x00 // b7-6:00, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
#define PTYPE_NULL_AT_HIGH_RATE 0x40 // b7-6:01, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
#define PTYPE_RESERVED 0x80 // b7-6:10
#define PTYPE_SPECIAL 0xc0 // b7-6:11
// when b7-6=11 (PTYPE_SPECIAL), b5-0 coube be ...
#define PSUBTYPE_DATA_NO_ACK 0x00
#define PSUBTYPE_MGMT 0x01
#define PSUBTYPE_OTHER_CNTL 0x02
#define PSUBTYPE_RTS 0x03
#define PSUBTYPE_MCU_INTERNAL 0x04
#endif
// value domain of pTxD->HostQId (4-bit: 0~15)
#define QID_AC_BK 1 // meet ACI definition in 802.11e
#define QID_AC_BE 0 // meet ACI definition in 802.11e
#define QID_AC_VI 2
#define QID_AC_VO 3
#define QID_HCCA 4
#define NUM_OF_TX_RING 5
#define QID_MGMT 13
#define QID_RX 14
#define QID_OTHER 15
//-----------------------------------------------------
// BBP & RF definition
//-----------------------------------------------------
#define BUSY 1
#define IDLE 0
#define BBP_R0 0 // version
#define BBP_R1 1 // TSSI
#define BBP_R2 2 // TX configure
#define BBP_R3 3
#define BBP_R4 4
#define BBP_R5 5
#define BBP_R6 6
#define BBP_R14 14 // RX configure
#define BBP_R16 16
#define BBP_R17 17 // RX sensibility
#define BBP_R18 18
#define BBP_R21 21
#define BBP_R22 22
#define BBP_R32 32
#define BBP_R62 62 // Rx SQ0 Threshold HIGH
#define BBP_R64 64
#define BBP_R66 66
#define BBP_R70 70 // Japan filter
#define BBP_R77 77
#define BBP_R82 82
#define BBP_R83 83
#define BBP_R84 84
#define BBP_R94 94 // Tx Gain Control
#define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
#define RSSI_FOR_LOW_SENSIBILITY -58
#define RSSI_FOR_MID_LOW_SENSIBILITY -66
#define RSSI_FOR_MID_SENSIBILITY -74
//-------------------------------------------------------------------------
// EEPROM definition
//-------------------------------------------------------------------------
#define EEDO 0x10
#define EEDI 0x08
#define EECS 0x04
#define EESK 0x02
#define EERL 0x01
#define EEPROM_WRITE_OPCODE 0x05
#define EEPROM_READ_OPCODE 0x06
#define EEPROM_EWDS_OPCODE 0x10
#define EEPROM_EWEN_OPCODE 0x13
#define NUM_EEPROM_BBP_PARMS 19
#define NUM_EEPROM_TX_G_PARMS 7
#define NUM_EEPROM_BBP_TUNING_PARMS 7
#define EEPROM_VERSION_OFFSET 0x2
#define EEPROM_MAC_ADDRESS_BASE_OFFSET 0x4
#define EEPROM_BBP_BASE_OFFSET 0x20
#define EEPROM_G_TX_PWR_OFFSET 0x46
#define EEPROM_FREQ_OFFSET 0x5e
#define EEPROM_LED_OFFSET 0x60
#define EEPROM_A_TX_PWR_OFFSET 0x62
#define EEPROM_J52_TX_PWR_OFFSET 0x7C //Skip 0x7C, it start from 0x7D
#define EEPROM_TSSI_REF_OFFSET 0x4A
#define EEPROM_TSSI_DELTA_OFFSET 0x1A
#define EEPROM_RSSI_BG_OFFSET 0x9a
#define EEPROM_RSSI_A_OFFSET 0x9c
#define EEPROM_BG_TSSI_CALIBRAION 0x54
#define EEPROM_A_TSSI_CALIBRAION 0x90
#define EEPROM_TXPOWER_DELTA_OFFSET 0x9e
// =================================================================================
// TX / RX ring descriptor format
// =================================================================================
// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
#define TXINFO_SIZE 24
//
// TX descriptor format, Tx ring, Mgmt Ring
//
#ifdef BIG_ENDIAN
typedef struct _TXD_STRUC {
} TXD_STRUC, *PTXD_STRUC;
#else
typedef struct _TXD_STRUC {
// word 0
ULONG Burst:1; // 1: Contiguously used current End Ponit, eg, Fragment packet should turn on.
// Tell EDCA that the next frame belongs to the same "burst" even though TXOP=0
ULONG Drop:1; // 0: skip this frame, 1:valid frame inside
ULONG MoreFrag:1; // 1: More fragment following this frame
ULONG ACK:1; // 1: ACK is required
ULONG Timestamp:1; // 1: MAC auto overwrite current TSF into frame body
ULONG Ofdm:1; // 1: TX using OFDM rates
ULONG IFS:1; // 1: require a BACKOFF before this frame, 0:SIFS before this frame
ULONG RetryMd:1; // 1: Long retry (4 times), 0: short retry (7 times)
ULONG TkipMic:1; // 1: ASIC is responsible for appending TKIP MIC if TKIP is inused
ULONG KeyTable:1; // 1: use per-client pairwise KEY table, 0: shared KEY table
ULONG KeyIndex:6; // Key index (0~31) to the pairwise KEY table; or
// 0~3 to shared KEY table 0 (BSS0). STA always use BSS0
// 4~7 to shared KEY table 1 (BSS1)
// 8~11 to shared KEY table 2 (BSS2)
// 12~15 to shared KEY table 3 (BSS3)
ULONG DataByteCnt:12;
ULONG Burst2:1; // definition as same as "Burst", for backward compatible set this one to the same as "Burst" set.
ULONG CipherAlg:3;
// Word 1
ULONG HostQId:4; // EDCA/HCCA queue ID
ULONG Aifsn:4;
ULONG Cwmin:4;
ULONG Cwmax:4;
ULONG IvOffset:6;
ULONG :6;
ULONG HwSeq:1; // MAC auto replace the 12-bit frame sequence #
ULONG BufCount:3; // number of buffers in this TXD
// Word 2
ULONG PlcpSignal:8;
ULONG PlcpService:8;
ULONG PlcpLengthLow:8;
ULONG PlcpLengthHigh:8;
// Word 3
ULONG Iv;
// Word 4
ULONG Eiv;
// Word 5
ULONG FrameOffset:8; // frame start offset inside ASIC TXFIFO (after TXINFO field)
ULONG PktId:8; // driver assigned packet ID to categorize TXResult in TxDoneInterrupt
ULONG BbpTxPower:8;
ULONG bWaitingDmaDoneInt:1; // pure s/w flag. 1:TXD been filled with data and waiting for TxDoneISR for housekeeping
ULONG Reserved:7;
// the above 24-byte is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
// The following fields are not used by MAC block. They are used by DMA block and HOST
// driver only. Once a frame has been DMA to ASIC, all the following fields are useless
// to ASIC.
} TXD_STRUC, *PTXD_STRUC;
#endif
//
// Rx descriptor format, Rx Ring
//
#ifdef BIG_ENDIAN
typedef struct _RXD_STRUC {
} RXD_STRUC, *PRXD_STRUC;
#else
typedef struct _RXD_STRUC {
// Word 0
ULONG Owner:1; // 1: owned by ASIC, 0: owned by HOST driver
ULONG Drop:1; // 1: drop without receiving to HOST
ULONG U2M:1; // 1: this RX frame is unicast to me
ULONG Mcast:1; // 1: this is a multicast frame
ULONG Bcast:1; // 1: this is a broadcast frame
ULONG MyBss:1; // 1: this frame belongs to the same BSSID
ULONG Crc:1; // 1: CRC error
ULONG Ofdm:1; // 1: this frame is received in OFDM rate
// ULONG PhyErr:1; // 1: this frame is received with PHY error
ULONG CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
ULONG KeyIndex:6; // decryption key actually used
ULONG DataByteCnt:12;
ULONG Rsv:1;
ULONG CipherAlg:3;
// word 1
ULONG PlcpSignal:8; // RX raw data rate reported by BBP
ULONG PlcpRssi:8; // RSSI reported by BBP
ULONG Rsv0:8;
ULONG FrameOffset:7;
ULONG Rsv1:1;
// Word 2
ULONG Iv; // received IV if originally encrypted; for replay attack checking
// Word 3
ULONG Eiv; // received EIV if originally encrypted; for replay attack checking
// word 4
ULONG Rsv2;
// The above 20-byte is called RXINFO and is prepared by MAC RX block and passed
// the HOST driver.
// The following fields are for DMA block and HOST usage only. Can't be touched
// by ASIC MAC block.
// Word 5
ULONG Rsv3; // BufPhyAddr;
#if 0
// Word 6~15
ULONG Rsv3;
ULONG Rsv4;
ULONG Rsv5;
ULONG Rsv6;
ULONG Rsv7;
ULONG Rsv8;
ULONG Rsv9;
ULONG Rsv10;
ULONG Rsv11;
ULONG Rsv12;
#endif
} RXD_STRUC, *PRXD_STRUC;
#endif
// =================================================================================
// HOST-MCU communication data structure
// =================================================================================
//
// H2M_MAILBOX_CSR: Host-to-MCU Mailbox
//
#ifdef BIG_ENDIAN
typedef union _H2M_MAILBOX_STRUC {
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -