/* * drivers/mmc/mmc.h * * header file for MMC device driver * * Copyright (C) 2001-2003 MIZI Research, Inc. * * Author: Yong-iL Joh <tolkien@mizi.com> * $Id: mmc.h,v 1.1.1.1 2004/01/19 13:24:45 laputa Exp $ * * Revision History: * * 2001-XX-XX Yong-iL Joh <tolkien@mizi.com> * - initial release * * 2002-07-25 Chan Gyun Jeong <cgjeong@mizi.com> * - code cleanup  *  * 2002-12-07 Chan Gyun Jeong <cgjeong@mizi.com> * - rough restructuring for S3C2410 SD Controller * * 2003-01-17 Chan Gyun Jeong <cgjeong@mizi.com> * - add slot mutex * */#ifndef MMC_MMC_H#define MMC_MMC_H#include <linux/types.h>#include <asm/semaphore.h>/* * MMC Legends *//*  PP		PushPull, output driver type with  		low impedance driver capability for 0 and 1  OD		OpenDrain, output driver type with  		low impedance driver capability for 0 and		high impedance driver capability for 1  bc		broadcast commands  bcr		broadcase commands with response  ac		addressed (point-to-point) commands (with resp.)  adtc		addressed (point-to-point) data transfer commands (with resp.)  CSD		CardSpecific data, MultiMediaCard register  		to store operating parameters  CID		Card IDentification Data, MultiMediaCard register		for ther card initialization procedure  RCA		Ralative Card Address, MultiMediaCard register		which contains the current card address of		an initialized MultiMediaCard  OCR		Operation Condition Register, MultiMediaCard register		which contains the voltage window		witch is supported by the MultiMediaCard  DSR		Driver Stage Register, control register  		for the programmable driver tge driver (PDS)  PDS		Porgrammable Driver Stage driver, is a tristate output driver  		which has is programmable to adapt		the driver capabilities to the bus design  CMD<n>	send command (48bit)  		47	0		start bit		46	1		host		45:40	bit5   .. bit0	command		39:8	bit31  .. bit0	argument		7:1	bit6   .. bit0	CRC7		0	1		end bit  R1		reponse command (48bit)  		47	0		start bit		46	0		card		45:40	bit5   .. bit0	command		39:8	bit31  .. bit0	status		7:1	bit6   .. bit0	CRC7		0	1		end bit  R1b		identical to R1 with the additional busy signaling via the data  R2		CID, CSD register (136bit)  		135	0		start bit		134	0		card		133:128	bit5   .. bit0	reserved		127:1	bit127 .. bit1	CID or CSD register					including internal CRC		0	1		end bit  R3		OCR register (48bit)  		47	0		start bit		46	0		card		45:40	bit5   .. bit0	reserved		39:8	bit31  .. bit0	OCR		7:1	bit6   .. bit0	reserved		0	1		end bit		0	1		end bit  dadr		Data Address  wadr		Write protect data Address  7-bit CRC	CRC7 (warning!!! it's a polynomical arithmetic mod 2)		G(x) = x^7 + x^3 + 1  		M(x) = (start bit)*x^39 + (host bit)*x^38 + ... +		       (last bit before CRC)*x^0		CRC[6..0] = Remainder[M(x)*x^7 / G(x)]*//* * MMC Commands *//* class 1, basic commands */#define	MMC_CMD0	0x40	/* bc, , , GO_IDLE_STATE */#define MMC_CMD1	0x41	/* bcr, 31:0 OCR, R3, SEND_OP_COND */#define MMC_CMD2	0x42	/* bcr, , R2, ALL_SEND_CID */#define MMC_CMD3	0x43	/* ac, 31:16 RCA, R1, SET_RELATIVE_ADDR */#define MMC_CMD4	0x44	/* bc, 31:16 RCA, , SET_DSR */#define MMC_CMD7	0x47	/* ac, 31:16 RCA, R1, SEELECT/DESELECT CARD */#define MMC_CMD9	0x49	/* ac, 31:16 RCA, R2, SEND_CSD */#define MMC_CMD10	0x4a	/* ac, 31:16 RCA, R2, SEND_CID */#define MMC_CMD11	0x4b	/* adtc, 31:0 dadr, R1, READ_DAT_UNTIL_STOP */#define MMC_CMD12	0x4c	/* ac, , R1b, STOP_TRANSMISSION */#define MMC_CMD13	0x4d	/* ac, 31:16 RCA, R1, SEND_STATUS */#define MMC_CMD15	0x4f	/* ac, 31:16 RCA, , GO_INACTIVE_SATE *//* class 2, block oriented read commands */#define MMC_CMD16	0x50	/* ac, 31:0 blk len, R1, SET_BLOCKLEN */#define MMC_CMD17	0x51	/* adtc, 31:0 dadr, R1, READ_SINGLE_BLOCK */#define MMC_CMD18	0x52	/* adtc, 31:0 dadr, R1, READ_MULTIPLE_BLOCK *//* class 3 */#define MMC_CMD20	0x54	/* adtc, 31:0 dadr, R1, WRITE_DAT_UNTIL_STOP *//* class 4, block oriented write commands */#define MMC_CMD24	0x58	/* adtc, 31:0 dadr, R1, WRITE_BLOCK */#define MMC_CMD25	0x59	/* adtc, 31:0 dadr, R1, WRITE_MULTIPLE_BLOCK */#define MMC_CMD26	0x5a	/* adtc, , R1, PROGRAM_CID */#define MMC_CMD27	0x5b	/* adtc, , R1, PROGRAM_CSD *//* class 6, block oriented write protection commands */#define MMC_CMD28	0x5c	/* ac, 31:0 dadr, R1b, SET_WRITE_PROT */#define MMC_CMD29	0x5d	/* ac, 31:0 dadr, R1b, CLR_WRITE_PROT */#define MMC_CMD30	0x5e	/* adtc, 31:0 wadr, R1, SEND_WRITE_PROT *//* class 5, erase commands */#define MMC_CMD32	0x60	/* ac, 31:0 dadr, R1, TAG_SECTOR_START */#define MMC_CMD33	0x61	/* ac, 31:0 dadr, R1, TAG_SECTOR_END */#define MMC_CMD34	0x62	/* ac, 31:0 dadr, R1, UNTAG_SECTOR */#define MMC_CMD35	0x63	/* ac, 31:0 dadr, R1, TAG_ERASE_GROUP_START */#define MMC_CMD36	0x64	/* ac, 31:0 dadr, R1, TAG_ERASE_GROUP_END */#define MMC_CMD37	0x65	/* ac, 31:0 dadr, R1, UNTAG_ERASE_GROUP */#define MMC_CMD38	0x66	/* ac, , R1b, ERASE *//* class 7, lock card */#define MMC_CMD42	0x6a	/* adtc, , R1b, LOCK_UNLOCK *//* class 8, applicatin specific commands */#define MMC_CMD55	0x77	/* ac, 31:16 RCA, R1, APP_CMD */#define MMC_CMD56	0x78	/* adtc, 0 RD/WR, R1, GEN_CMD  *//*APP CMD*/#define MMC_ACMD42	0x69	/* bcr, 31:0 OCR, R3, SEND_OP_COND *//* Command size */#define MMC_CMD_SIZE	6/* Command timings */#define	MMC_TIME_NCR_MIN	2	/* min. of Number of cycles					   between command and response */#define MMC_TIME_NCR_MAX	64	/* max. of Number of cycles					   between command and response */#define MMC_TIME_NID_MIN	5	/* min. of Number of cycles					   between card identification or					   card operation conditions command					   and the corresponding response */#define MMC_TIME_NID_MAX	10	/* max. of Number of cycles					   between card identification or					   card operation conditions command					   and the corresponding response */#define MMC_TIME_NAC_MIN	2	/* min. of Number of cycles					   between command and 					   the start of a related data block */#define MMC_TIME_NRC_MIN	8	/* min. of Number of cycles					   between the last reponse and					   a new command */#define MMC_TIME_NCC_MIN	8	/* min. of Number of cycles					   between two commands, if no reponse					   will be send after the first command					   (e.g. broadcast) */#define MMC_TIME_NWR_MIN	2	/* min. of Number of cycles					   between a write command and					   the start of a related data block *//*  * CID(Card IDentification) Register  */typedef struct {	__u8  mid;	/* Manufacturer ID */	__u16 oid;	/* OEM/Application ID */	__u8  pnm[7];	/* Product Name + '\0', MMC only */	__u8  prv;	/* Product Version */	__u32 psn;	/* Product Serial Number */	__u8  mdt;	/* Manufacturing date, MMC only */} CID_regs;#define MMC_CID_SIZE	16/*  * OCR (Operation Condition Register) */typedef __u32 OCR_regs;#define MMC_OCR_SIZE	4#define MMC_VDD_20_36	0x00ffff00	/* VDD voltage 2.0 ~ 3.6 */#define MMC_VDD_27_36	0x00ff8000	/* VDD voltage 2.0 ~ 3.6 */#define MMC_VDD_20_21	0x00000100	/* VDD voltage 2.0 ~ 2.1 */#define MMC_VDD_21_22	0x00000200	/* VDD voltage 2.1 ~ 2.2 */#define MMC_VDD_22_23	0x00000400	/* VDD voltage 2.2 ~ 2.3 */#define MMC_VDD_23_24	0x00000800	/* VDD voltage 2.3 ~ 2.4 */#define MMC_VDD_24_25	0x00001000	/* VDD voltage 2.4 ~ 2.5 */#define MMC_VDD_25_26	0x00002000	/* VDD voltage 2.5 ~ 2.6 */#define MMC_VDD_26_27	0x00004000	/* VDD voltage 2.6 ~ 2.7 */#define MMC_VDD_27_28	0x00008000	/* VDD voltage 2.7 ~ 2.8 */#define MMC_VDD_28_29	0x00010000	/* VDD voltage 2.8 ~ 2.9 */#define MMC_VDD_29_30	0x00020000	/* VDD voltage 2.9 ~ 3.0 */#define MMC_VDD_30_31	0x00040000	/* VDD voltage 3.0 ~ 3.1 */#define MMC_VDD_31_32	0x00080000	/* VDD voltage 3.1 ~ 3.2 */#define MMC_VDD_32_33	0x00100000	/* VDD voltage 3.2 ~ 3.3 */#define MMC_VDD_33_34	0x00200000	/* VDD voltage 3.3 ~ 3.4 */#define MMC_VDD_34_35	0x00400000	/* VDD voltage 3.4 ~ 3.5 */#define MMC_VDD_35_36	0x00800000	/* VDD voltage 3.5 ~ 3.6 */#define MMC_nCARD_BUSY	0x80000000	/* Card Power up status bit *//*  * Relative Card Address  */typedef __u16 RCA_regs;#define MMC_RCA_SIZE	2/*  * CSD register, rwe == read/write/erase  */typedef struct {	__u8 csd;		/* CSD structure */	__u8 spec_vers;		/* Spec version, MMC only */	struct {		__u8 man;	/* time mantissa */		__u8 exp;	/* time exponent */	} taac;			/* Data read access-time-1 */	__u8 nsac;		/* Data read access-time-2 in CLK cycle */	struct {		__u8 man;	/* rate mantissa */		__u8 exp;	/* rate exponent */	} tran_speed;		/* Max. data transfer rate */	__u16 ccc;		/* Card command classes */	__u8 read_len;		/* Max. read data block length */	__u8 read_part;		/* Partial blocks for read allowed */	__u8 write_mis;		/* write block misalignment */	__u8 read_mis;		/* read block misalignment */	__u8 dsr;		/* DSR implemented */	__u16 c_size;		/* Device size */	__u8 vcc_r_min;		/* Max. read current at Vcc min */	__u8 vcc_r_max;		/* Max. read current at Vcc max */	__u8 vcc_w_min;		/* Max. write current at Vcc min */	__u8 vcc_w_max;		/* Max. write current at Vcc max */	__u8 c_size_mult;	/* Device size multiplier */	__u8 er_size;		/* Erase sector size, MMC only */	__u8 er_grp_size;	/* Erase group size, MMC only */	__u8 wp_grp_size;	/* Write protect group size */	__u8 wp_grp_en;		/* Write protect group enable */	__u8 dflt_ecc;		/* Manufacturer default ECC, MMC only */	__u8 r2w_factor;	/* Write speed factor */	__u8 write_len;		/* Max. write data block length */	__u8 write_part;	/* Partial blocks for write allowed */	__u8 ffmt_grp;		/* File format group, rw */	__u8 copy;		/* Copy flag (OTP), rw */	__u8 perm_wp;		/* Permanent write protection, rw */	__u8 tmp_wp;		/* temporary write protection, rwe */	__u8 ffmt;		/* file format, rw */	__u8 ecc;		/* ECC, rwe, MMC only */} CSD_regs;#define MMC_CSD_SIZE	16#define CSD_VERSION_10	0#define CSD_VERSION_11	1#define MMC_PROT_10	0	/* MMC protocol version 1.0 - 1.2 */#define MMC_PROT_14	1	/* MMC protocol version 1.4 */#define TAAC_EXP_1NS	0	/* 1ns */#define TAAC_EXP_10NS	1	/* 10ns */#define TAAC_EXP_100NS	2	/* 100ns */#define TAAC_EXP_1UMS	3	/* 1 u-ms */#define TAAC_EXP_10UMS	4	/* 10 u-ms */#define TAAC_EXP_100UMS	5	/* 100 u-ms */#define TAAC_EXP_1MS	6	/* 1ms */#define TAAC_EXP_10MS	7	/* 10ms */#define TIME_MAN_NONE	0	/* reserved */#define TIME_MAN_10	1	/* 1.0 */#define TIME_MAN_12	2	/* 1.2 */