?? myproj.vhd

?? candence工程文件
?? VHD
?? 第 1 頁 / 共 4 頁
字號:
12 3 4 下一頁
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY SCHEMATIC1 IS 

END SCHEMATIC1;



ARCHITECTURE STRUCTURE OF SCHEMATIC1 IS

-- COMPONENTS

COMPONENT \15K\
	PORT (
	\1\ : INOUT std_logic;
	\2\ : INOUT std_logic
	); END COMPONENT;

COMPONENT RS4
	PORT (
	\1\ : INOUT std_logic;
	\2\ : INOUT std_logic;
	\3\ : INOUT std_logic;
	\4\ : INOUT std_logic;
	\5\ : INOUT std_logic;
	\6\ : INOUT std_logic;
	\7\ : INOUT std_logic;
	\8\ : INOUT std_logic
	); END COMPONENT;

COMPONENT NE5532
	PORT (
	\AIN-\ : IN std_logic;
	\AIN+\ : IN std_logic;
	AOUT : OUT std_logic;
	VCC : IN std_logic;
	GND : IN std_logic;
	\BIN+\ : IN std_logic;
	\BIN-\ : IN std_logic;
	BOUT : OUT std_logic
	); END COMPONENT;

COMPONENT \EMI FILTER\
	PORT (
	I : IN std_logic;
	GND : IN std_logic;
	O : OUT std_logic
	); END COMPONENT;

COMPONENT \100nF\
	PORT (
	\1\ : INOUT std_logic;
	\2\ : INOUT std_logic
	); END COMPONENT;

COMPONENT \1uF\
	PORT (
	\1\ : INOUT std_logic;
	\2\ : INOUT std_logic
	); END COMPONENT;

COMPONENT CS4272
	PORT (
	XTO : INOUT std_logic;
	XTI : INOUT std_logic;
	MCCLK : INOUT std_logic;
	LRCK : INOUT std_logic;
	SCLK : INOUT std_logic;
	SDOUT : OUT std_logic;
	SDIN : IN std_logic;
	DGND : IN std_logic;
	VD : IN std_logic;
	VL : IN std_logic;
	\SCL/CCLK\ : IN std_logic;
	\SDA/CDIN\ : INOUT std_logic;
	\AD0/C\\S\\\ : IN std_logic;
	\R\\S\\T\\\ : IN std_logic;
	VCOM : IN std_logic;
	\AINA-\ : IN std_logic;
	\AINA+\ : IN std_logic;
	\AINB+\ : IN std_logic;
	\AINB-\ : IN std_logic;
	VA : IN std_logic;
	AGND : IN std_logic;
	\FILT+\ : INOUT std_logic;
	\A\\M\\U\\T\\E\\C\\\ : OUT std_logic;
	\AOUTA-\ : OUT std_logic;
	\AOUTA+\ : OUT std_logic;
	\AOUTB+\ : OUT std_logic;
	\AOUTB-\ : OUT std_logic;
	\B\\M\\U\\T\\E\\C\\\ : OUT std_logic
	); END COMPONENT;

COMPONENT AMS1117_3V3
	PORT (
	\GND/ADJ\ : IN std_logic;
	VOUT : IN std_logic;
	VIN : IN std_logic;
	TAB : IN std_logic
	); END COMPONENT;

COMPONENT CLOCK
	PORT (
	NC : INOUT std_logic;
	GND : IN std_logic;
	CLK : OUT std_logic;
	VCC : IN std_logic
	); END COMPONENT;

COMPONENT CY2303
	PORT (
	REF : OUT std_logic;
	GND : IN std_logic;
	REFIN : IN std_logic;
	NC : INOUT std_logic;
	REF2 : OUT std_logic;
	REF4 : OUT std_logic;
	VDD : IN std_logic;
	OE : INOUT std_logic
	); END COMPONENT;

COMPONENT TMS320C6713GDP
	PORT (
	ED0 : INOUT std_logic;
	ED1 : INOUT std_logic;
	ED2 : INOUT std_logic;
	ED3 : INOUT std_logic;
	ED4 : INOUT std_logic;
	ED5 : INOUT std_logic;
	ED6 : INOUT std_logic;
	ED7 : INOUT std_logic;
	ED8 : INOUT std_logic;
	ED9 : INOUT std_logic;
	ED10 : INOUT std_logic;
	ED11 : INOUT std_logic;
	ED12 : INOUT std_logic;
	ED13 : INOUT std_logic;
	ED14 : INOUT std_logic;
	ED15 : INOUT std_logic;
	EA2 : OUT std_logic;
	EA3 : OUT std_logic;
	EA4 : OUT std_logic;
	EA5 : OUT std_logic;
	EA6 : OUT std_logic;
	EA7 : OUT std_logic;
	EA8 : OUT std_logic;
	EA9 : OUT std_logic;
	EA10 : OUT std_logic;
	EA11 : OUT std_logic;
	EA12 : OUT std_logic;
	EA13 : OUT std_logic;
	EA14 : OUT std_logic;
	EA15 : OUT std_logic;
	EA16 : OUT std_logic;
	EA17 : OUT std_logic;
	EA18 : OUT std_logic;
	EA19 : OUT std_logic;
	EA20 : OUT std_logic;
	EA21 : OUT std_logic;
	\C\\E\\0\\\ : OUT std_logic;
	\C\\E\\1\\\ : OUT std_logic;
	\C\\E\\2\\\ : OUT std_logic;
	\C\\E\\3\\\ : OUT std_logic;
	\B\\E\\0\\\ : OUT std_logic;
	\B\\E\\1\\\ : OUT std_logic;
	\H\\O\\L\\D\\A\\\ : OUT std_logic;
	\H\\O\\L\\D\\\ : IN std_logic;
	BUSREQ : OUT std_logic;
	ECLKIN : IN std_logic;
	ECLKOUT : OUT std_logic;
	\AR\\E\\/SD\\C\\A\\S\\/SS\\A\\D\\S\\\ : OUT std_logic;
	\AO\\E\\/SD\\R\\A\\S\\/SS\\O\\E\\\ : OUT std_logic;
	\AW\\E\\/SD\\W\\E\\/SS\\W\\E\\\ : OUT std_logic;
	ARDY : IN std_logic;
	ED16 : INOUT std_logic;
	ED17 : INOUT std_logic;
	ED18 : INOUT std_logic;
	ED19 : INOUT std_logic;
	ED20 : INOUT std_logic;
	ED21 : INOUT std_logic;
	ED22 : INOUT std_logic;
	ED23 : INOUT std_logic;
	ED24 : INOUT std_logic;
	ED25 : INOUT std_logic;
	ED26 : INOUT std_logic;
	ED27 : INOUT std_logic;
	ED28 : INOUT std_logic;
	ED29 : INOUT std_logic;
	ED30 : INOUT std_logic;
	ED31 : INOUT std_logic;
	\B\\E\\2\\\ : INOUT std_logic;
	\B\\E\\3\\\ : INOUT std_logic;
	\HD15/GP[15]\ : INOUT std_logic;
	\HD14/GP[14]\ : INOUT std_logic;
	\HD13/GP[13]\ : INOUT std_logic;
	\HD7/GP[3]\ : INOUT std_logic;
	\HD3/AMUTE1\ : INOUT std_logic;
	\H\\I\\N\\T\\/GP[1]\ : INOUT std_logic;
	\HD4/GP[0]\ : INOUT std_logic;
	\HD12/GP[12]\ : INOUT std_logic;
	\HD11/GP[11]\ : INOUT std_logic;
	\HD10/GP[10]\ : INOUT std_logic;
	\HD9/GP[9]\ : INOUT std_logic;
	\HD8/GP[8]\ : INOUT std_logic;
	\HD6/AHCKR1\ : INOUT std_logic;
	\HD5/AHCKX1\ : INOUT std_logic;
	\HD1/AXR1[7]\ : INOUT std_logic;
	\HD2/AFSX1\ : INOUT std_logic;
	\HD0/AXR1[4]\ : INOUT std_logic;
	\HCNTL1/AXR1[1]\ : IN std_logic;
	\HCNTL0/AXR1[3]\ : IN std_logic;
	\HHWIL/AFSR1\ : IN std_logic;
	\HR/W\\/AXR1[0]\ : IN std_logic;
	\H\\A\\S\\/ACLKX1\ : IN std_logic;
	\H\\R\\D\\Y\\/ACLKR1\ : INOUT std_logic;
	\H\\D\\S\\2\\/AXR1[5]\ : IN std_logic;
	\H\\D\\S\\1\\/AXR1[6]\ : IN std_logic;
	\HCS/AXR1[2]\ : IN std_logic;
	\R\\E\\S\\E\\T\\\ : IN std_logic;
	NMI : IN std_logic;
	\GP[7]/(EXT_INT7)\ : INOUT std_logic;
	\GP[6]/(EXT_INT6)\ : INOUT std_logic;
	\GP[5]/(EXT_INT5)/AMUTEIN0\ : INOUT std_logic;
	\GP[4]/(EXT_INT4)/AMUTEIN1\ : INOUT std_logic;
	\TOUT1/AXR0[4]\ : INOUT std_logic;
	\TINP1/AHCLKX0\ : INOUT std_logic;
	\TOUT0/AXR0[2]\ : INOUT std_logic;
	\TINP0/AXR0[3]\ : INOUT std_logic;
	CLKIN : IN std_logic;
	\CLOKOUT2/GP[2]\ : INOUT std_logic;
	CLKOUT3 : OUT std_logic;
	CLKMODE0 : IN std_logic;
	PLLHV : IN std_logic;
	TMS : IN std_logic;
	TDO : OUT std_logic;
	TDI : IN std_logic;
	TCK : IN std_logic;
	\T\\R\\S\\T\\\ : IN std_logic;
	EMU1 : INOUT std_logic;
	EMU0 : INOUT std_logic;
	EMU2 : INOUT std_logic;
	EMU3 : INOUT std_logic;
	EMU4 : INOUT std_logic;
	EMU5 : INOUT std_logic;
	\CLKX1/AMUTE0\ : INOUT std_logic;
	FSX1 : INOUT std_logic;
	\DX1/AXR0[5]\ : OUT std_logic;
	\CLKR1/AXR0[6]\ : INOUT std_logic;
	\FSR1/AXR0[7]\ : INOUT std_logic;
	\DR1/SDA1\ : IN std_logic;
	\CLKS1/SCL1\ : IN std_logic;
	\CLKX0/ACLKX0\ : INOUT std_logic;
	\FSX0/AFSX0\ : INOUT std_logic;
	\DX0/AXR0[1]\ : OUT std_logic;
	\CLKR0/ACLKR0\ : INOUT std_logic;
	\FSR0/AFSR0\ : INOUT std_logic;
	\DR0/AXR0[0]\ : IN std_logic;
	\CLKS0/AHCLKR0\ : IN std_logic;
	SCL0 : INOUT std_logic;
	SDA0 : INOUT std_logic;
	DVDD1 : IN std_logic;
	DVDD2 : IN std_logic;
	DVDD3 : IN std_logic;
	DVDD4 : IN std_logic;
	DVDD5 : IN std_logic;
	DVDD6 : IN std_logic;
	DVDD7 : IN std_logic;
	DVDD8 : IN std_logic;
	DVDD9 : IN std_logic;
	DVDD10 : IN std_logic;
	DVDD12 : IN std_logic;
	DVDD13 : IN std_logic;
	DVDD14 : IN std_logic;
	DVDD15 : IN std_logic;
	DVDD16 : IN std_logic;
	DVDD17 : IN std_logic;
	DVDD18 : IN std_logic;
	DVDD19 : IN std_logic;
	DVDD20 : IN std_logic;
	DVDD11 : IN std_logic;
	RSV1 : INOUT std_logic;
	RSV2 : INOUT std_logic;
	RSV3 : INOUT std_logic;
	RSV4 : INOUT std_logic;
	RSV5 : INOUT std_logic;
	RSV6 : INOUT std_logic;
	CVDD_32 : IN std_logic;
	CVDD_31 : IN std_logic;
	CVDD_30 : IN std_logic;
	CVDD_29 : IN std_logic;
	CVDD_28 : IN std_logic;
	CVDD_27 : IN std_logic;
	CVDD_26 : IN std_logic;
	CVDD_25 : IN std_logic;
	CVDD_24 : IN std_logic;
	CVDD_23 : IN std_logic;
	CVDD_22 : IN std_logic;
	CVDD_21 : IN std_logic;
	CVDD_20 : IN std_logic;
	CVDD_19 : IN std_logic;
	CVDD_18 : IN std_logic;
	CVDD_17 : IN std_logic;
	CVDD_16 : IN std_logic;
	CVDD_15 : IN std_logic;
	CVDD_14 : IN std_logic;
	CVDD_13 : IN std_logic;
	CVDD_12 : IN std_logic;
	CVDD_11 : IN std_logic;
	CVDD_10 : IN std_logic;
	CVDD_9 : IN std_logic;
	CVDD_8 : IN std_logic;
	CVDD_7 : IN std_logic;
	CVDD_6 : IN std_logic;
	CVDD_5 : IN std_logic;
	CVDD_4 : IN std_logic;
	CVDD_3 : IN std_logic;
	CVDD_2 : IN std_logic;
	CVDD_1 : IN std_logic;
	DVDD21 : IN std_logic;
	DVDD22 : IN std_logic;
	DVDD23 : IN std_logic;
	DVDD24 : IN std_logic;
	DVDD25 : IN std_logic;
	DVDD26 : IN std_logic;
	DVDD27 : IN std_logic;
	RSV7 : OUT std_logic;
	VSS0 : IN std_logic;
	VSS1 : IN std_logic;
	VSS2 : IN std_logic;
	VSS3 : IN std_logic;
	VSS4 : IN std_logic;
	VSS5 : IN std_logic;
	VSS6 : IN std_logic;
	VSS7 : IN std_logic;
	VSS8 : IN std_logic;
	VSS9 : IN std_logic;
	VSS10 : IN std_logic;
	VSS11 : IN std_logic;
	VSS12 : IN std_logic;
	VSS13 : IN std_logic;
	VSS14 : IN std_logic;
	VSS15 : IN std_logic;
	VSS16 : IN std_logic;
	VSS17 : IN std_logic;
	VSS18 : IN std_logic;
	VSS19 : IN std_logic;
	VSS20 : IN std_logic;
	VSS21 : IN std_logic;
	VSS22 : IN std_logic;
	VSS23 : IN std_logic;
	VSS24 : IN std_logic;
	VSS25 : IN std_logic;
	VSS26 : IN std_logic;
	VSS27 : IN std_logic;
	VSS28 : IN std_logic;
	VSS29 : IN std_logic;
	VSS30 : IN std_logic;
	VSS31 : IN std_logic;
	VSS32 : IN std_logic;
	VSS33 : IN std_logic;
	VSS34 : IN std_logic;
	VSS35 : IN std_logic;
	VSS36 : IN std_logic;
	VSS37 : IN std_logic;
	VSS38 : IN std_logic;
	VSS39 : IN std_logic;
	VSS40 : IN std_logic;
	VSS41 : IN std_logic;
	VSS42 : IN std_logic;
	VSS43 : IN std_logic;
	VSS44 : IN std_logic;
	VSS45 : IN std_logic;
	VSS46 : IN std_logic;
	VSS47 : IN std_logic;
	VSS48 : IN std_logic;
	VSS49 : IN std_logic;
	VSS50 : IN std_logic;
	VSS51 : IN std_logic;
	VSS52 : IN std_logic;
	VSS53 : IN std_logic;
	VSS54 : IN std_logic;
	VSS55 : IN std_logic;
	VSS56 : IN std_logic;
	VSS57 : IN std_logic;
	VSS58 : IN std_logic;
	VSS59 : IN std_logic;
	VSS60 : IN std_logic;
	VSS61 : IN std_logic;
	VSS62 : IN std_logic;
	VSS63 : IN std_logic;
	VSS64 : IN std_logic;
	VSS65 : IN std_logic;
	VSS66 : IN std_logic;
	VSS67 : IN std_logic;
	VSS68 : IN std_logic
	); END COMPONENT;

COMPONENT FB
	PORT (
	\1\ : INOUT std_logic;
	\2\ : INOUT std_logic
	); END COMPONENT;

COMPONENT \MT48LC2M32B2B5-6\
	PORT (
	DQ0 : INOUT std_logic;
	DQ1 : INOUT std_logic;
	DQ2 : INOUT std_logic;
	DQ3 : INOUT std_logic;
	DQ4 : INOUT std_logic;
	DQ5 : INOUT std_logic;
	DQ6 : INOUT std_logic;
	DQ7 : INOUT std_logic;
	DQ8 : INOUT std_logic;
	DQ9 : INOUT std_logic;
	DQ10 : INOUT std_logic;
	DQ11 : INOUT std_logic;
	DQ12 : INOUT std_logic;
	DQ13 : INOUT std_logic;
	DQ14 : INOUT std_logic;
	DQ15 : INOUT std_logic;
	DQ16 : INOUT std_logic;
	DQ17 : INOUT std_logic;
	DQ18 : INOUT std_logic;
	DQ19 : INOUT std_logic;
	DQ20 : INOUT std_logic;
	DQ21 : INOUT std_logic;
	DQ22 : INOUT std_logic;
	DQ23 : INOUT std_logic;
	DQ24 : INOUT std_logic;
	DQ25 : INOUT std_logic;
	DQ26 : INOUT std_logic;
	DQ27 : INOUT std_logic;
	DQ28 : INOUT std_logic;
	DQ29 : INOUT std_logic;
	DQ30 : INOUT std_logic;
	DQ31 : INOUT std_logic;
	A0 : IN std_logic;
	A1 : IN std_logic;
	A2 : IN std_logic;
	A3 : IN std_logic;
	A4 : IN std_logic;
	A5 : IN std_logic;
	A6 : IN std_logic;
	A7 : IN std_logic;
	A8 : IN std_logic;
	A9 : IN std_logic;
	A10 : IN std_logic;
	BA0 : IN std_logic;
	BA1 : IN std_logic;
	DQM0 : IN std_logic;
	DQM1 : IN std_logic;
	DQM2 : IN std_logic;
	DQM3 : IN std_logic;
	CLK : IN std_logic;
	CKE : IN std_logic;
	\CS#\ : IN std_logic;
	\WE#\ : IN std_logic;
	\CAS#\ : IN std_logic;
	\RAS#\ : IN std_logic;
	VDDQ0 : IN std_logic;
	VDDQ1 : IN std_logic;
	VDDQ2 : IN std_logic;
	VDDQ3 : IN std_logic;
	VDDQ4 : IN std_logic;
	VDDQ5 : IN std_logic;
	VDDQ6 : IN std_logic;
	VDDQ7 : IN std_logic;
	VSSQ0 : IN std_logic;
	VSSQ1 : IN std_logic;
	VSSQ2 : IN std_logic;
	VSSQ3 : IN std_logic;
	VSSQ4 : IN std_logic;
	VSSQ5 : IN std_logic;
	VSSQ6 : IN std_logic;
	VSSQ7 : IN std_logic;
	VDD_1 : IN std_logic;
	VDD_15 : IN std_logic;
	VDD_29 : IN std_logic;
	VDD_43 : IN std_logic;
	VSS_44 : IN std_logic;
	VSS_58 : IN std_logic;
	VSS_72 : IN std_logic;
	VSS_86 : IN std_logic;
	NC0 : IN std_logic;
	NC1 : IN std_logic;
	NC2 : IN std_logic;
	NC3 : IN std_logic;
	NC4 : IN std_logic;
	NC5 : IN std_logic;
	NC6 : IN std_logic
	); END COMPONENT;

COMPONENT SST39VF800A
	PORT (
	A1 : IN std_logic;
	A2 : IN std_logic;
	A3 : IN std_logic;
	A4 : IN std_logic;
	A5 : IN std_logic;
	A6 : IN std_logic;
	A7 : IN std_logic;
	A8 : IN std_logic;
	A9 : IN std_logic;
	A10 : IN std_logic;
	A11 : IN std_logic;
	A12 : IN std_logic;
	A13 : IN std_logic;
	A14 : IN std_logic;
	A15 : IN std_logic;
	A16 : IN std_logic;
	A17 : IN std_logic;
	A18 : IN std_logic;
	DQ0 : INOUT std_logic;
	DQ1 : INOUT std_logic;
	DQ2 : INOUT std_logic;
	DQ3 : INOUT std_logic;
	DQ4 : INOUT std_logic;
	DQ5 : INOUT std_logic;
	DQ6 : INOUT std_logic;
	DQ7 : INOUT std_logic;
	DQ8 : INOUT std_logic;
	DQ9 : INOUT std_logic;
	DQ10 : INOUT std_logic;
	DQ11 : INOUT std_logic;
	DQ12 : INOUT std_logic;
	DQ13 : INOUT std_logic;
	DQ14 : INOUT std_logic;
	DQ15 : INOUT std_logic;
	A0 : IN std_logic;
	\CE#\ : IN std_logic;
	\OE#\ : IN std_logic;
	\WE#\ : IN std_logic;
	VDD : IN std_logic;
	VSS_27 : IN std_logic;
	VSS_46 : IN std_logic;
	NC1 : INOUT std_logic;
	NC2 : INOUT std_logic;
	NC7 : INOUT std_logic;
	NC3 : INOUT std_logic;
	NC4 : INOUT std_logic;
	NC5 : INOUT std_logic;
	NC6 : INOUT std_logic
	); END COMPONENT;

COMPONENT CON4
	PORT (
	\1\ : INOUT std_logic;
	\2\ : INOUT std_logic;
	\3\ : INOUT std_logic;
	\4\ : INOUT std_logic
	); END COMPONENT;

COMPONENT \HEADER 7X2\
	PORT (
	\2\ : INOUT std_logic;
	\4\ : INOUT std_logic;
	\6\ : INOUT std_logic;
	\8\ : INOUT std_logic;
	\10\ : INOUT std_logic;
	\12\ : INOUT std_logic;
	\14\ : INOUT std_logic;
	\1\ : INOUT std_logic;
	\3\ : INOUT std_logic;
	\5\ : INOUT std_logic;
	\7\ : INOUT std_logic;
	\9\ : INOUT std_logic;
	\11\ : INOUT std_logic;
	\13\ : INOUT std_logic
	); END COMPONENT;

COMPONENT JTAG
	PORT (
	TMS : OUT std_logic;
	TDI : OUT std_logic;
	PD_VCC : IN std_logic;
	TDO : IN std_logic;
	TCK_RET : IN std_logic;
	TCK : OUT std_logic;
	EMU0 : INOUT std_logic;
	EMU1 : INOUT std_logic;
	GND_12 : IN std_logic;
	GND_10 : IN std_logic;
	GND_8 : IN std_logic;
	GND_4 : IN std_logic;
	\T\\R\\S\\T\\\ : OUT std_logic;
	NC : INOUT std_logic
	); END COMPONENT;

COMPONENT \HEADER 5X2\
	PORT (
	\2\ : INOUT std_logic;
	\4\ : INOUT std_logic;
	\6\ : INOUT std_logic;
	\8\ : INOUT std_logic;
	\10\ : INOUT std_logic;
	\1\ : INOUT std_logic;
	\3\ : INOUT std_logic;
	\5\ : INOUT std_logic;
	\7\ : INOUT std_logic;
	\9\ : INOUT std_logic
	); END COMPONENT;

COMPONENT LED
	PORT (
	ANODE : INOUT std_logic;
	CATHODE : INOUT std_logic
	); END COMPONENT;

COMPONENT \HEADER 6X2\
	PORT (
	\2\ : INOUT std_logic;
	\4\ : INOUT std_logic;
	\6\ : INOUT std_logic;
	\8\ : INOUT std_logic;
	\10\ : INOUT std_logic;
	\12\ : INOUT std_logic;
	\1\ : INOUT std_logic;
	\3\ : INOUT std_logic;
	\5\ : INOUT std_logic;
	\7\ : INOUT std_logic;
	\9\ : INOUT std_logic;
	\11\ : INOUT std_logic
	); END COMPONENT;

COMPONENT AUDIO_RJ
	PORT (
	GND : IN std_logic;
	R : INOUT std_logic;
	L : INOUT std_logic;
	NCR : INOUT std_logic;
	NCL : INOUT std_logic
	); END COMPONENT;

COMPONENT \DSP-RESET\
	PORT (
	\1\ : INOUT std_logic;
	\3\ : INOUT std_logic;
	\2\ : INOUT std_logic;
	\4\ : INOUT std_logic
	); END COMPONENT;

-- SIGNALS

SIGNAL CLKR1 : std_logic;
SIGNAL TAB : std_logic;
SIGNAL N75509 : std_logic;
SIGNAL LIN : std_logic;
SIGNAL N73968 : std_logic;
SIGNAL N10780 : std_logic;
SIGNAL N73916 : std_logic;
SIGNAL N43972 : std_logic;
SIGNAL N93029 : std_logic;
SIGNAL N43908 : std_logic;
SIGNAL N52922 : std_logic;
SIGNAL N66431 : std_logic;
SIGNAL RIN : std_logic;
SIGNAL N81989 : std_logic;
SIGNAL N44000 : std_logic;
SIGNAL N92923 : std_logic;
SIGNAL N60492 : std_logic;
SIGNAL N73672 : std_logic;
SIGNAL N59644 : std_logic;
SIGNAL LOUT : std_logic;
SIGNAL N73984 : std_logic;
SIGNAL N61739 : std_logic;
SIGNAL N91553 : std_logic;
SIGNAL N11845 : std_logic;
SIGNAL N11082 : std_logic;
SIGNAL N73692 : std_logic;
SIGNAL N43948 : std_logic;
12 3 4 下一頁
?? 文件大小 4197 K
?? 上傳用戶 mtzhy2
?? 所屬分類 PCB相關
??? 相關標簽

#candence #工程
?? 快捷鍵說明

復制代碼 Ctrl + C
搜索代碼 Ctrl + F
全屏模式 F11
切換主題 Ctrl + Shift + D
顯示快捷鍵 ?
增大字號 Ctrl + =
減小字號 Ctrl + -
亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

?? myproj.vhd

?? 快捷鍵說明
