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Date: Tue, 26 Nov 1996 18:51:10 GMTServer: NCSA/1.5MIME-version: 1.0Content-type: text/htmlLast-modified: Mon, 12 Feb 1996 23:08:56 GMTContent-length: 3128<HTML><HEAD> <TITLE>CSE 521: Computer Architecture</TITLE></HEAD><BODY><H1></H1><H1><CENTER><!WA0><IMG SRC="http://wizard.cse.nd.edu/class_data/cse521/www/Images/image3.gif" WIDTH="462" HEIGHT="90" ALIGN=bottom NATURALSIZEFLAG="3"></CENTER></H1><H1>CSE 521: Computer Architecture</H1><P><CENTER><HR></CENTER><H3>Class Meeting Time and Place:</H3><BLOCKQUOTE><B>Lecture:</B><BR>Tuesday, Thursday 1:15-2:30 PM<BR>155 DeBartolo Hall<BR><BR><B>Lab:</B><BR>Tuesday, Wednesday, or Thursday 2:45-4:15<BR>254 Fitzpatrick Hall</BLOCKQUOTE><H3>Instructor:</H3><BLOCKQUOTE>Dr. Jay B. Brockman<BR>352 Fitzpatrick Hall<BR>x1-8810<BR><!WA1><A HREF="http://wizard.cse.nd.edu/class_data/cse521/www/jbb@cse.nd.edu">jbb@cse.nd.edu</A></BLOCKQUOTE><HR><H3>Course Description:<BR><BR><HR><BR>Text:</H3><BLOCKQUOTE>J.L. Hennessy and D.A. Patterson<BR><I>Computer Architecture: A Quantitative Approach, 2nd edition</I><BR>Morgan Kaufmann Publishers, San Francisco, 1996</BLOCKQUOTE><H3>Lecture Notes:</H3><H4>CSE 322: Undergraduate Computer Architecture II</H4><UL><LI><!WA2><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/Introduction.ps">Introduction</A><LI><!WA3><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/HardwareFirmware.ps">Hardware/FirmwareImplementation of Algorithms</A> <LI><!WA4><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/ControlPath.ps">Hardware/FirmwareImplementation of Control</A> <LI><!WA5><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/SingleCycle.ps">TheSingle-Cycle MIPS Processor </A><LI><!WA6><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/MultiCycle.ps">TheMultiple Cycle MIPS Processor </A><LI><!WA7><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/Pipeline.ps">Pipelining</A><LI><!WA8><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/Hazards.ps">PipeliningContinued: Hazards </A><LI><!WA9><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/Cache.ps">MemoryHierarchy </A><LI><!WA10><A HREF="http://www.cse.nd.edu/class_data/cse322/classnotes/InputOutput.ps">InterfacingProcessors, Peripherals, and Memory </A></UL><H4>New Lecture Notes for This Course</H4><BR><!WA11><IMG SRC="http://wizard.cse.nd.edu/class_data/cse521/www/Images/construction.gif" WIDTH="40" HEIGHT="40" ALIGN=middle NATURALSIZEFLAG="3"><B>Under Construction</B> <H3>Homework and Design Projects:</H3><UL><LI>Homework 1: Hardware/Firmware Implementation of Algorithms due 2/2/96<LI>Homework 2: Control System Design due 2/2/96 <LI>Homework 3: Processor Metrics and Instructions Set Architecture, Hennessy& Patterson exercises 1.1, 1.4, 1.7, 1.14, 2.1, 2.3, 2.10, 2.11, due2/20/96</UL><H3>Newsgroups:</H3><UL><LI><!WA12><A HREF="news:nd.courses.cse521">nd.courses.cse521</A> newsgroup forthis course <LI><!WA13><A HREF="news:nd.courses.cse322">nd.courses.cse322 </A>newsgroup forthe undergraduate architecture course <LI><!WA14><A HREF="news:nd.cse.mentor">nd.cse.mentor</A> questions and answerson the Mentor Graphics CAD tools </UL><H3>Other Useful Links:</H3><BR><!WA15><IMG SRC="http://wizard.cse.nd.edu/class_data/cse521/www/Images/construction.gif" WIDTH="40" HEIGHT="40" ALIGN=middle NATURALSIZEFLAG="3"><B>Under Construction</B><ADDRESS><!WA16><A HREF="http://wizard.cse.nd.edu/class_data/cse521/www/Jay.B.Brockman.1@nd.edu">Jay.B.Brockman.1@nd.edu</A></ADDRESS><BR>Last Modified: 1/24/96 </BODY></HTML>?? 快捷鍵說明
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