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Date: Tue, 05 Nov 1996 00:16:21 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Fri, 13 Sep 1996 15:33:22 GMTContent-length: 18153<HTML> <HEAD> <title> Andy Glew's Resume </title> </HEAD> <BODY> <H1> <center><bold> <BIG> Andy Glew </BIG> </bold> </center> </H1> <center> 412 West Shore Drive <br> Madison, WI 53715 <br> <br> Home: 503-693-9830 <br> <code> glew@cs,wisc.edu glew@ichips.intel.com </code> </center> <h2>Career Goals</h2> <ul> <li>Challenging hardware/software development. <li>To design the next generation of high-performance microprocessor, going beyond out-of-order dynamic execution and instruction level parallelism towards meso-scale parallelism. <li>To apply the technical management concepts that can create a "Breakthrough System" for creative work like Computer Architecture; to recreate Thomas Edison's "Invention Factory" in the modern world. </ul> <h2>Skills</h2> <dl> <dt><b>Performance Tuning and Analysis</b><dd> <ul> <li>Both hardware and software. <li><em>I can make anything run faster!</em> </ul> <dt><b>Hardware</b><dd> <ul> <li>High-performance computer architecture, especially out-of-order microarchitectures. <li>Parallel processors <li>Synchronization <li>Cache and Bus Protocols <li>Memory Consistency Models <li>Super-scalar Processors <li>Behavioural and structural modelling in RTLs (register transfer languages) such as iHDL (Intel Hardware Description Language). <li>Computer arithmetic, particularly redundant forms to increase performance. </ul> <dt><b>Software</b><dd> <ul> <li>OS: UNIX System V and BSD 4.3 kernel. Some NT kernel. Win95 drivers. <li>Programming Languages: C, LISP used regularly. Familiar with C++, COBOL, FORTRAN, PASCAL, PL/1. <li>Assembly Languages: 680x0, 88K, 80x86, Gould PN and NP, MIPS R2000, PowerPC. <li>Environments: super-micro to mini-super. </ul> </dl> <h2>Education</h2> <ul> <li>August 1996 - date: Ph.D. student at the University of Wisconsim, Madison. Advisor: Guri Sohi. <!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/~glew/generic-PhD-research-interests.html"> Research interests: </A> more aggressive out-of-order, superscalar, dynamic execution, CPUs. <li>September 1987 - January 1991: University of Illinois at Urbana Champaign, M.Sc. in Electrical and Computer Engineering. Thesis: "Synchronization Primitive Implementation including the Bus Abandonment Lock" Advisor: Wen-mei Hwu. Subject area: computer architecture, parallel processing, synchronization instructions, cache and bus protocols. Other research: super scalar processing (register renaming, minimal control dependencies). Part time before January 1990 (while working at Gould and Motorola). GPA 4.8/5. <li>1980-1985: McGill University, Montreal, Bachelor of Engineering in Electrical Engineering (Computer Option). GPA 2.87/4. Projects include: RAMM/RISC/SEISM - a Reduced Addressing Mode, RISC, Small Efficient Instruction Set Machine. <li>1978-1980: Marianopolis College, Montreal, Diplome des Etudes Collegiales. </ul> <h2>Employment</h2> <dl> <dt>January 1991-date: Intel Corporation, Hillsboro, Oregon<dd> <P> <DL> <dt>August 1996-date: <b>Student</b><dd> Although I continue to be affiliated with Intel's Microcomputer Research Labs - e.g. I am still covered by the Intel NDA, and will work at Intel on breaks - I am now mainly a full time student pursuing my Ph.D. <dt>November 1995-August 1996: <b>Computer Architect/Researcher</b>, Microcomputer Research Labs; Leader, Intel Architecture CPU Research Group<dd> <P> <B>Manager</B>: Richard Wirt (Intel Fellow). </P> <p> I agreed tp spend approximately one year (prior to returning to school to finish my Ph.D.) helping to get this research group off the ground, defining the research directions hiring 5 Ph.D. level researchers (and trying to hire more), and budgetting and arranging capital purchases of approximately 500,000$ in computer equipment and services. <p> <dt>January 1991-November 1995: <b>Computer Architect</b>, P6.<dd> <P> <B>Managers</B>: Bob Colwell (1991-1993), Dave Papworth (1993-1995). </P> <ul> <li>One of five architects involved in the <B>Original P6 Microarchitecture Definition</B> (in 1991) and supported design by providing oversight and making global tradeoffs throughout the life of the project. <ul> <li>Defined top-level interface between subsystems. <li>Defined execution unit "uop" instruction set. <li>Defined microcode format. <li>Significant contributions to design of non-blocking cache. <li>Defined and performed initial RTL coding of branch mechanism, including interfaces between BTB and execution units. <li>Simulation studies to simplify logic involved in retirement of branches. <li>Defined global control register bus. </ul> <li>After initial definition phase led <B>P6 HW/SW Codevelopment</B> team (up to 3 full time engineers, 3 students) <ul> <li>Wrote <B>P6 External Architecture Specification.</B> Defined all new architecturally visible features (Machine Check, mechanisms for reducing TLB invalidations, memory types) and new instructions (conditional moves, fast system calls). <li>Liaison between P6 Architecture and software groups: <B>compilers</B>, <B>OSes</B> (Intel and Microsoft), assembly language applications such as <B> multimedia, video, 3D graphics, and games </B> developers. <li>Wrote <B>P6 Code Tuning</B> Guide. <li>Defined new memory types that increase memory to <b>framebuffer</b> performance by 4-7X. <li>Defined and supervised <b>block memory fill and copy optimizations</b>, including inventing a new cache protocol that reduces memory traffic by 50-30%. <li><B>Tuned code</B>, including a single, notorious, optimization that improved iSPEC92 by approximately 25%. Supervising recent work improving branch predictability. Supervising much work improving performance analysis tools for code tuning. <li>Defined P6 <B>Performance Monitoring</B> hardware (EMON). Defined and supervised development of software (UNIX and Windows) to perform <B>EMON profiling</B>, a new method of performance analysis involving statistical sampling of code locations associated with particular performance problems. <li>Defined and supervised development of <B>Priviliged Mode Execution (PMX)</B> device driver, on UNIX on Microsoft OSes, permitting access to many hardware priviliged facilities from user code, facilitating automation of many performance and validation testing procedures. <li>Initially defined and supervised development of <B>API Profiling</B> device drivers on Windows 3.1, which permitted investigation of performance issues not just by flat code location, but also according to call tree. Supervised first application of this tool to tuning computer games and 3D graphics applications. </ul> <li>Acted as an x86 architecture expert, frequently representing P6 to Intel's <B>Compatibility Architecture Review Team (CART).</B> <ul> <li>Creator and keeper of the official Intel x86 Instruction Set Definition, on behalf of CART. <li>CART expert on APIC (interrupt controller) architecture. <li>CART expert on SMM (System Management Mode). </ul> <li>Original investigator of x86 instruction set enhancements to support multimedia, video, and graphics; P6 representative on <B>MMX</B> definition effort; key inventions that permit instruction set enhancement without OS changes. <li>P6 representative in evaluation of future instruction set architectures. <li>Future x86 microarchitectures. <li>Member of Intel Research Council's Natural Datatypes Technical Committee, supervising research in multimedia, graphics, speech and handwriting recognition, etc. </ul> </DL> </P> <dt>January 1990-May 1990: <b>Teaching Assistant</b> Foundations for <b>VLSI Design</b> Automation<dd> <P> Course CS497-LGJ taught by Professor Larry Jones, at AT&T Bell Labs Naperville (Indian Hill). University of Illinois at Urbana-Champaign, Department of Computer Science.?? 快捷鍵說明
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