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Date: Tue, 05 Nov 1996 00:25:42 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Thu, 31 Aug 1995 22:55:22 GMTContent-length: 3994<HTML><HEAD><TITLE>Vortex: Semi-custom hardware for a Typhoon prototype </title></HEAD><BODY><H1>Vortex/Typhoon-Zero</H1><P><hr>Vortex is a standard-width MBUS board designed to work with a dualhyperSparc processor module. It provides tag services on up to 128M ofphysical memory, as well as a dispatch mechanism for message andmemory block access fault handler code.<p><p>When installed in each <!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/~wwt/cow.html">COW</A> node, Vortex willallow Tempest codes to run with hardware assisted block accesscontrol/message dispatch, which allows memory to be shared on acache-line (32-byte) basis across nodes. The <!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><A HREF="http://www.cs.wisc.edu/~wwt/cow.html">COW</A> + Vortex isreferred to as Typhoon-Zero, and is intended as a prototype/feasibilty study for Typhoon, a more sophisticated hardware platform for Tempest codes. Theboard does not implement any kind of DSM protocol; instead it provideshardware assistance for the Tempest mechanisms, giving the user thefreedom to implement whatever policies are desired.<P>Here is a paper describing more than you ever wanted to know about Vortex:<ul><li><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.cs.wisc.edu/~pfile/vortex/vortex_report.ps"><b>PostScript (1.6MB)</b></a> (beware, 150 pages!)<li><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.cs.wisc.edu/~pfile/vortex/vortex_report.ps.gz"><b>Gzipped PostScript (347KB),</b></a> (150 pages!)<li><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href="http://www.cs.wisc.edu/~pfile/vortex/vortex_report_noappendix.ps"><b>PostScript (1.4MB)</b></a> (no source code; 60 pages)<li><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><a href="http://www.cs.wisc.edu/~pfile/vortex/vortex_report_noappendix.ps.gz"><b>Gzipped PostScript (302KB),</b></a> (no source code; 60 pages)<li><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><a href="http://www.cs.wisc.edu/~pfile/vortex/vort_rep.sit.hqx"><b>BinHexed Stuffed PostScript (Macintosh) (412KB)</b></a> (no source code; 60 pages)<li><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><a href="http://www.cs.wisc.edu/~pfile/vortex/paper_noappendix/paper_noappendix.html"><b>HTML (Browseable Online Version)</b></a> (no source code)</ul><p><em> Sorry Windoze & DOS lunatics, no .lzh or .zip here! </em><P>Status<P><ul><li>Verilog code started, Sep 94<li>Initial Vortex logic finished (verilog), Nov 94<li>Intra-FPGA timing goals met Nov 94 <li>Repartitioned for inter-FPGA timing, Dec 94<li>Exhaustive simulation testing (against Viking model) Jan-Feb 95<li>PC board design Feb-Mar 95<li>4 boards fabbed 21 Mar 95<li>1 board stuffed (minus FPGAs) 22 Mar 95<li>Clock generation circuits test OK 22 Mar 95<li>Test on hold; waiting for FPGAs<li>5 FPGAs delivered from Altera 4 Apr 95<li>Final board assembly 5 Apr 95<li>PLL bug fixed 5 Apr 95<li>Good test of uncacheable registers & tags 5 Apr 95<li>Good test of cacheable registers & master CI 6 Apr 95<li>Good test of master CRI (user tag downgrade) 7 Apr 95<li>Good test of Tempest snooping (CR to RO/Inv only) 7 Apr 95<li>schip msh_ bug fixed 8 Apr 95<li>Good test of all Vortex functions against hyperSparc in SS-10 12 Apr 95<li>Good test against hyperSparc in SS-20 (50MHz) 17 Apr 95<li>Random test program exposes snooping bug, fixed 28 Apr 95<li>Snooping bug fix creates block buffer bug, fixed 6 May 95<li>Board passes random test 9 May 95<li>Second board built 10 May 95<li>Second board passes random test 11 May 95<li>Working Tempest port to Typhoon-Zero (<!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><a href="http://www.cs.wisc.edu/~stever"><b>Steve Reinhardt</b></a>) 3 Jun 95</ul><p>Pictures<P><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><img src="http://www.cs.wisc.edu/~pfile/vortex/vortex_sm.gif"><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><a href="http://www.cs.wisc.edu/~pfile/vortex/vortex_crop.gif"> Click here for alarge picture of the bare Vortex board.</a><P><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><img src="http://www.cs.wisc.edu/~pfile/vortex/vor2_sm.gif"><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><a href="http://www.cs.wisc.edu/~pfile/vortex/vor2.gif"> Click here for alarge picture of the partially-stuffed prototype board.</a><P><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><img src="http://www.cs.wisc.edu/~pfile/vortex/vortex_sn001_revA_modB_sm.gif"><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><a href="http://www.cs.wisc.edu/~pfile/vortex/vortex_sn001_revA_modB.gif"> This is Vortex Rev. A, S/N 001, Mod Level B.</a><P>Thanks to Soeren Christensen for the pictures. <P><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><a href="http://www.cs.wisc.edu/~pfile"> back to rob pfile's home page</a><p><HR><ADDRESS> Last Changed: 30 Aug 95 </ADDRESS><HR></BODY></HTML>?? 快捷鍵說明
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