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<TITLE>B441/B541 Lab Syllabus for Fall, 1996</TITLE><CENTER><H1>Digital Design B441/B541<BR>Lab Syllabus for Fall, 1996</H1></CENTER><HR><H2>Contents</H2><UL><LI><!WA0><A HREF="#AI">Associate Instructor</A><LI><!WA1><A HREF="#NEWS">Newsgroup</A><LI><!WA2><A HREF="#FORMAT">Format of the Lab</A><LI><!WA3><A HREF="#GRADING">Laboratory Grading</A><LI><!WA4><A HREF="#LABINFO">Lab Info</A><LI><!WA5><A HREF="#LABSCHEDULE">Lab Schedule</A></UL><HR><A NAME="AI"><H2>Your Friendly AI</H2></A><UL><LI><!WA6><A HREF="http://www.cs.indiana.edu/hyplan/davwils.html">David Wilson</A><UL> <LI>Office: Lindley Hall 406 (x5-8702)<LI>Office Hours: Tuesday 12-1, Wednesday 10-11<LI>E-mail: <!WA7><A HREF="mailto:davwils@cs.indiana.edu">davwils@cs.indiana.edu</A></UL></LI></UL><HR><A NAME="NEWS"><H2>Newsgroup</H2></A>A newsgroup has been set up for this course:<!WA8><A HREF="news:ac.csci.b441">ac.csci.b441</A>.It is recommended that you post all questions to this newsgroup.If <EM>you</EM> want to know the answer to a question, chances aresomeone else does, too.Also, if you know the answer to a question someone has posted, weencourage you to post your answer and discuss the possiblesolutions. <P>All of this, of course, assumes you are following the guidelines onacademic honesty. <P><HR><A NAME="FORMAT"><H2>Format of the Lab</H2></A>For the first nine weeks of the lab (except for the first lab), therewill be an assignment due at the beginning of each lab. The assignmentwill typically consist of both written work and a working circuit onyour logic engine. Since the PDP-8 is such a wiring intensive project,it will be divided into three parts with extended deadlines. Inaddition to the lab assignments, you will be given a laboratory examrelating to the PDP-8. This exam will come at the end of the semesterand will test for practical, in-depth knowledge of your circuit. <P>Please note that, in general, you will be working in pairs.All written exercises are to be handed in individually and will begraded as individual work. You and your partner will co-operate on allcircuits, however, and will be given a single grade for yourcircuitry. Because wiring experience will be shared, it is<EM>your</EM> responsibility to make sure you understand what wiringyour partner has done and to make sure that you are doing your fairshare. You may divide up the work however you and your partner prefer,but if we see that one of you is consistently not doing enough work,we may re-arrange the groups. <P><HR><A NAME="GRADING"><H2>Laboratory Grading</H2></A>The <EM>lab</EM> grade will be broken down in the following way:<UL><LI> 75% -- Lab assignments<LI> 10% -- Working PDP-8<LI> 15% -- Final exam</UL><HR><A NAME="LABINFO"><H2>Lab Info</H2></A><UL><LI><!WA9><A HREF="http://www.cs.indiana.edu./classes/c421/man/man.html">       Software Tools Documentation (man pages)</A><LI><!WA10><A HREF="file://www.cs.indiana.edu./classes/b441//nfs/paca/u/b441/pub/chipmunk/b441-diglog.cnf">       Sample <CODE>diglog</CODE> configuration file</A> <LI><!WA11><A HREF="http://www.cs.indiana.edu/classes/b441/diglog-stuff.html">       Getting Started with Diglog </A> <LI><!WA12><A HREF="http://www.cs.indiana.edu/classes/b441/manasm.html">       Manual ASM Control of PDP-8, Lab 10 </A> <LI><!WA13><A HREF="http://www.cs.indiana.edu/classes/b441/pdp8.txt">       PDP-8 FAQ </A> <LI><!WA14><A HREF="http://www.cs.uiowa.edu/~jones/pdp8/index.html">       Other PDP-8 Info on the Web </A> </UL><HR><A NAME="LABSCHEDULE"></A><CENTER><TABLE BORDER=10 CELLPADDING=10><TR><TH COLSPAN=3><H2>Laboratory Schedule<BR>                  Digital Design B441/B541<BR>                  Fall '96</H2></TH></TR><TR><TD><CENTER><STRONG>Week of</STRONG></CENTER></TD><TD><CENTER><STRONG>Manual Section</STRONG></CENTER></TD><TD><CENTER><STRONG>Topic</STRONG></CENTER></TD></TR><TR><TD>September 3</TD><TD>Lab 1</TD><TD>Introduction to laboratory equipment and procedures.  Simulation.</TD></TR><TR><TD>September 10</TD><TD>|</TD><TD>|</TD></TR><TR><TD>September 17</TD><TD>Lab 2</TD><TD>Mixed Logic</TD></TR><TR><TD>September 24</TD><TD>Lab 3</TD><TD>Three-state logic</TD></TR><TR><TD>|</TD><TD>Lab 4</TD><TD>Programmable logic and PLDs</TD></TR><TR><TD>October 1</TD><TD>Lab 5</TD><TD>Synthesis of combinational elements -- muxes, encoders, comparators</TD></TR><TR><TD>October 8</TD><TD>Lab 6</TD><TD>An ALU</TD></TR><TR><TD>October 15</TD><TD>Lab 7</TD><TD>Sequential circuits -- counters</TD></TR><TR><TD>October 22</TD><TD>Lab 8</TD><TD>Register-transfer concepts</TD></TR><TR><TD>October 29</TD><TD>Lab 9</TD><TD>Building the PDP-8 data-path PALs</TD></TR><TR><TD>|</TD><TD>Lab 10</TD><TD>Manual ASM control of the PDP-8</TD></TR><TR><TD>|</TD><TD>Lab 11</TD><TD>Building the PDP-8 controller</TD></TR><TR><TD>November 5</TD><TD>|</TD><TD>|</TD></TR><TR><TD>November 12</TD><TD>|</TD><TD>|</TD></TR><TR><TD>November 19</TD><TD>|</TD><TD>| (By this week, you should have completed the design and wiring of your PDP-8 processor, and should have installed and wired the supplied I/O interface.)</TD></TR><TR><TD>November 26</TD><TD><PRE> </PRE></TD><TD><EM>Thanksgiving Recess</EM></TD></TR><TR><TD>December 3</TD><TD>Lab 12</TD><TD>Debugging and testing the PDP-8 processor</TD></TR><TR><TD>December 10</TD><TD>---</TD><TD>Final PDP-8 test and lab checkout</TD></TR><TR><TD>December 16</TD><TD><PRE> </PRE></TD><TD><EM>Finals Week -- no scheduled lab activity</EM></TD></TR></TABLE></CENTER><BR><HR><!WA15><A HREF="http://www.cs.indiana.edu/hyplan/davwils.html"><ADDRESS>dcw 8/27/96</ADDRESS></A>