LISTING FOR LOGIC DESCRIPTION FILE: GATES.pld                        Page 1

CUPL(WM): Universal Compiler for Programmable Logic
Version 4.8a Serial# MW-45466466
Copyright (c) 1983, 1996 Logical Devices, Inc.
Created Sun Mar 19 11:41:37 2000

  1:Name            Gates;
  2:Partno          CA0001;
  3:Revision        04;
  4:Date            9/12/89;
  5:Designer        G. Woolhiser;
  6:Company         Logical Devices, Inc.;
  7:Location        None;
  8:Assembly        None;
  9:Device          g16v8a;
 10:
 11:/****************************************************************/
 12:/*                                                              */
 13:/*      This is a example to demonstrate how CUPL               */
 14:/*      compiles simple gates.                                  */
 15:/*                                                              */
 16:/****************************************************************/
 17:
 18:/*
 19: * Inputs:  define inputs to build simple gates from
 20: */
 21:
 22:Pin 1 =  a;
 23:Pin 2 =  b;
 24:
 25:/*
 26: * Outputs:  define outputs as active HI levels
 27: *
 28: */
 29:
 30:Pin 12 = inva;
 31:Pin 13 = invb;
 32:Pin 14 = and;
 33:Pin 15 = nand;
 34:Pin 16 = or;
 35:Pin 17 = nor;
 36:Pin 18 = xor;
 37:Pin 19 = xnor;
 38:
 39:/*
 40: * Logic:  examples of simple gates expressed in CUPL
 41: */
 42:
 43:inva = !a;              /* inverters */
 44:invb = !b;
 45:and  = a & b;           /* and gate */
 46:nand = !(a & b);        /* nand gate */
 47:or   = a # b;           /* or gate */
 48:nor  = !(a # b);        /* nor gate */
 49:xor  = a $ b;           /* exclusive or gate */
 50:xnor = !(a $ b);        /* exclusive nor gate */
 51:
 52:
 53:

LISTING FOR LOGIC DESCRIPTION FILE: GATES.pld                        Page 2

CUPL(WM): Universal Compiler for Programmable Logic
Version 4.8a Serial# MW-45466466
Copyright (c) 1983, 1996 Logical Devices, Inc.
Created Sun Mar 19 11:41:37 2000

 54:
 55:



Jedec Fuse Checksum       (3a6b)
Jedec Transmit Checksum   (d98f)