// Bit set //
.DEFINE CB_TMR0_TGAIF					0	
.DEFINE CB_TMR0_TGBIF					1
.DEFINE CB_TMR0_TGCIF					2	
.DEFINE CB_TMR0_TPRIF					3
.DEFINE CB_TMR0_TCVIF					4
.DEFINE CB_TMR0_TCUIF					6	
.DEFINE CB_TMR0_TCDF					7	
.DEFINE CB_TMR0_PDCIF					8

// P_TMR1_Status register //
// word set //
.DEFINE CW_TMR1_TGAIF_Enable			0x0001	
.DEFINE CW_TMR1_TGBIF_Enable			(0x0001 << 1)	
.DEFINE CW_TMR1_TGCIF_Enable			(0x0001 << 2)	
.DEFINE CW_TMR1_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR1_TCVIF_Enable			(0x0001 << 5)	
.DEFINE CW_TMR1_TCUIF_Enable			(0x0001 << 6)	
.DEFINE CW_TMR1_TCDF_Enable				(0x0001 << 7)	
.DEFINE CW_TMR1_PDCIF_Enable			(0x0001 << 8)	

// Bit set //
.DEFINE CB_TMR1_TGAIF					0	
.DEFINE CB_TMR1_TGBIF					1	
.DEFINE CB_TMR1_TGCIF					2
.DEFINE CB_TMR1_TPRIF					3	
.DEFINE CB_TMR1_TCVIF					4	
.DEFINE CB_TMR1_TCUIF					5
.DEFINE CB_TMR1_TCDF					6	
.DEFINE CB_TMR1_PDCIF					7

// P_TMR2_Status register //
// word set //
.DEFINE CW_TMR2_TGAIF_Enable			0x0001	
.DEFINE CW_TMR2_TGBIF_Enable			(0x0001 << 1)	
.DEFINE CW_TMR2_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR2_TCDF_Enable				(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR2_TGAIF_Enable			0	
.DEFINE CB_TMR2_TGBIF_Enable			1
.DEFINE CB_TMR2_TPRIF_Enable			4
.DEFINE CB_TMR2_TCDF_Enable				7

// P_TMR3_Status register //
// word set //
.DEFINE CW_TMR3_TGDIF_Enable			(0x0001 << 3)	
.DEFINE CW_TMR3_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR3_TCDF_Enable				(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR3_TGDIF_Enable			3	
.DEFINE CB_TMR3_TPRIF_Enable			4	
.DEFINE CB_TMR3_TCDF_Enable				7

// P_TMR4_Status register //
// word set //
.DEFINE CW_TMR4_TGDIF_Enable			(0x0001 << 3)	
.DEFINE CW_TMR4_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR4_TCDF_Enable				(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR4_TGDIF_Enable			3
.DEFINE CB_TMR4_TPRIF_Enable			4
.DEFINE CB_TMR4_TCDF_Enable				7

// P_TMR_Start register //
// word set //
.DEFINE CW_TMR_TMR0ST_Start				0x0001	
.DEFINE CW_TMR_TMR1ST_Start				(0x0001 << 1)	
.DEFINE CW_TMR_TMR2ST_Start				(0x0001 << 2)	
.DEFINE CW_TMR_TMR3ST_Start				(0x0001 << 3)	
.DEFINE CW_TMR_TMR4ST_Start				(0x0001 << 4)	

// Bit set //
.DEFINE CB_TMR_TMR0ST_Start				0	
.DEFINE CB_TMR_TMR1ST_Start				1	
.DEFINE CB_TMR_TMR2ST_Start				2
.DEFINE CB_TMR_TMR3ST_Start				3
.DEFINE CB_TMR_TMR4ST_Start				4

// P_TMR_Output register //
// word set //
.DEFINE CW_TMR_TMR3AOE_Enable			0x0001
.DEFINE CW_TMR_TMR3BOE_Enable			(0x0001 << 1)
.DEFINE CW_TMR_TMR3COE_Enable			(0x0001 << 2)
.DEFINE CW_TMR_TMR3DOE_Enable			(0x0001 << 3)
.DEFINE CW_TMR_TMR3EOE_Enable			(0x0001 << 4)
.DEFINE CW_TMR_TMR3FOE_Enable			(0x0001 << 5)
.DEFINE CW_TMR_TMR4AOE_Enable			(0x0001 << 8)
.DEFINE CW_TMR_TMR4BOE_Enable			(0x0001 << 9)
.DEFINE CW_TMR_TMR4COE_Enable			(0x0001 << 10)
.DEFINE CW_TMR_TMR4DOE_Enable			(0x0001 << 11)
.DEFINE CW_TMR_TMR4EOE_Enable			(0x0001 << 12)
.DEFINE CW_TMR_TMR4FOE_Enable			(0x0001 << 13)

// Bit set //
.DEFINE CB_TMR_TMR3AOE_Enable			0
.DEFINE CB_TMR_TMR3BOE_Enable			1
.DEFINE CB_TMR_TMR3COE_Enable			2
.DEFINE CB_TMR_TMR3DOE_Enable			3
.DEFINE CB_TMR_TMR3EOE_Enable			4
.DEFINE CB_TMR_TMR3FOE_Enable			5
.DEFINE CB_TMR_TMR4AOE_Enable			8
.DEFINE CB_TMR_TMR4BOE_Enable			9
.DEFINE CB_TMR_TMR4COE_Enable			10
.DEFINE CB_TMR_TMR4DOE_Enable			11
.DEFINE CB_TMR_TMR4EOE_Enable			12
.DEFINE CB_TMR_TMR4FOE_Enable			13

// P_TMR3_OutputCtrl register //
// word set //
.DEFINE CW_TMR3_UOC_Mode0				0x0000	
.DEFINE CW_TMR3_UOC_Mode1				0x0001
.DEFINE CW_TMR3_UOC_Mode2				0x0002
.DEFINE CW_TMR3_UOC_Mode3				0x0003
.DEFINE CW_TMR3_VOC_Mode0				(0x0000 << 2)	
.DEFINE CW_TMR3_VOC_Mode1				(0x0001 << 2)
.DEFINE CW_TMR3_VOC_Mode2				(0x0002 << 2)
.DEFINE CW_TMR3_VOC_Mode3				(0x0003 << 2)
.DEFINE CW_TMR3_WOC_Mode0				(0x0000 << 4)	
.DEFINE CW_TMR3_WOC_Mode1				(0x0001 << 4)
.DEFINE CW_TMR3_WOC_Mode2				(0x0002 << 4)
.DEFINE CW_TMR3_WOC_Mode3				(0x0003 << 4)
.DEFINE CW_TMR3_SYNC_NoSync				(0x0000 << 6)	
.DEFINE CW_TMR3_SYNC_PDR				(0x0001 << 6)	
.DEFINE CW_TMR3_SYNC_TGB				(0x0002 << 6)	
.DEFINE CW_TMR3_SYNC_TGC				(0x0003 << 6)	
.DEFINE CW_TMR3_UPWM_Out_HL				(0x0000 << 8)	
.DEFINE CW_TMR3_UPWM_Out_PWM			(0x0001 << 8)	
.DEFINE CW_TMR3_VPWM_Out_HL				(0x0000 << 9)	
.DEFINE CW_TMR3_VPWM_Out_PWM			(0x0001 << 9)	
.DEFINE CW_TMR3_WPWM_Out_HL				(0x0000 << 10)
.DEFINE CW_TMR3_WPWM_Out_PWM			(0x0001 << 10)
.DEFINE CW_TMR3_POLP_Active_Low			(0x0000 << 14)
.DEFINE CW_TMR3_POLP_Active_High		(0x0001 << 14)
.DEFINE CW_TMR3_DUTYMODE_UCom			(0x0000 << 15)
.DEFINE CW_TMR3_DUTYMODE_Independent	(0x0001 << 15)

// Bit set //
.DEFINE CB_TMR3_UOC0					0	
.DEFINE CB_TMR3_UOC1					1
.DEFINE CB_TMR3_VOC0					2	
.DEFINE CB_TMR3_VOC1					3
.DEFINE CB_TMR3_WOC0					4	
.DEFINE CB_TMR3_WOC1					5
.DEFINE CB_TMR3_SYNC0					6	
.DEFINE CB_TMR3_SYNC1					7		
.DEFINE CB_TMR3_UPWM					8	
.DEFINE CB_TMR3_VPWM					9	
.DEFINE CB_TMR3_WPWM					10
.DEFINE CB_TMR3_POLP_Active				14
.DEFINE CB_TMR3_DUTYMODE				15

// POLP = 1 //
.DEFINE CW_TMR3_POLP_1_UP_CPWM_UN_PWM			(CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_1_UP_L_UN_PWM				(CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_PWM)				
.DEFINE CW_TMR3_POLP_1_UP_PWM_UN_L				(CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_1_UP_PWM_UN_CPWM			(CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_PWM)

.DEFINE CW_TMR3_POLP_1_VP_CPWM_VN_PWM			(CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_1_VP_L_VN_PWM				(CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_PWM)				
.DEFINE CW_TMR3_POLP_1_VP_PWM_VN_L				(CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_1_VP_PWM_VN_CPWM			(CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_PWM)

.DEFINE CW_TMR3_POLP_1_WP_CPWM_WN_PWM			(CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_1_WP_L_WN_PWM				(CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_PWM)				
.DEFINE CW_TMR3_POLP_1_WP_PWM_WN_L				(CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_1_WP_PWM_WN_CPWM			(CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_PWM)

.DEFINE CW_TMR3_POLP_1_UP_L_UN_L				(CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_UP_L_UN_H				(CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_UP_H_UN_L				(CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_UP_H_UN_H				(CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_HL)

.DEFINE CW_TMR3_POLP_1_VP_L_VN_L				(CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_VP_L_VN_H				(CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_VP_H_VN_L				(CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_VP_H_VN_H				(CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_HL)

.DEFINE CW_TMR3_POLP_1_WP_L_WN_L				(CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_WP_L_WN_H				(CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_WP_H_WN_L				(CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_HL)
.DEFINE CW_TMR3_POLP_1_WP_H_WN_H				(CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_HL)

// POLP = 0 //
.DEFINE CW_TMR3_POLP_0_UP_PWM_UN_CPWM			(CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_UP_H_UN_CPWM				(CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_UP_CPWM_UN_H				(CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_UP_CPWM_UN_PWM			(CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_PWM)

.DEFINE CW_TMR3_POLP_0_VP_PWM_VN_CPWM			(CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_VP_H_VN_CPWM				(CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_VP_CPWM_VN_H				(CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_VP_CPWM_VN_PWM			(CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_PWM)

.DEFINE CW_TMR3_POLP_0_WP_PWM_WN_CPWM			(CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_WP_H_WN_CPWM				(CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_WP_CPWM_WN_H				(CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_PWM)
.DEFINE CW_TMR3_POLP_0_WP_CPWM_WN_PWM			(CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_PWM)

.DEFINE CW_TMR3_POLP_0_UP_H_UN_H				(CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_UP_H_UN_L				(CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_UP_L_UN_H				(CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_UP_L_UN_L				(CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_HL)

.DEFINE CW_TMR3_POLP_0_VP_H_VN_H				(CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_VP_H_VN_L				(CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_VP_L_VN_H				(CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_VP_L_VN_L				(CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_HL)

.DEFINE CW_TMR3_POLP_0_WP_H_WN_H				(CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_WP_H_WN_L				(CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_WP_L_WN_H				(CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_HL)
.DEFINE CW_TMR3_POLP_0_WP_L_WN_L				(CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_HL)


// P_TMR4_OutputCtrl register //
// word set //
.DEFINE CW_TMR4_UOC_Out1				0x0000	
.DEFINE CW_TMR4_UOC_Out2				0x0001
.DEFINE CW_TMR4_UOC_Out3				0x0002
.DEFINE CW_TMR4_UOC_Out4				0x0003
.DEFINE CW_TMR4_VOC_Out1				(0x0000 << 2)	
.DEFINE CW_TMR4_VOC_Out2				(0x0001 << 2)
.DEFINE CW_TMR4_VOC_Out3				(0x0002 << 2)
.DEFINE CW_TMR4_VOC_Out4				(0x0003 << 2)
.DEFINE CW_TMR4_WOC_Out1				(0x0000 << 4)	
.DEFINE CW_TMR4_WOC_Out2				(0x0001 << 4)
.DEFINE CW_TMR4_WOC_Out3				(0x0002 << 4)
.DEFINE CW_TMR4_WOC_Out4				(0x0003 << 4)
.DEFINE CW_TMR4_SYNC_NoSync				(0x0000 << 6)	
.DEFINE CW_TMR4_SYNC_PDR				(0x0001 << 6)	
.DEFINE CW_TMR4_SYNC_TGB				(0x0002 << 6)	
.DEFINE CW_TMR4_SYNC_TGC				(0x0003 << 6)	
.DEFINE CW_TMR4_UPWM_Out_HL				(0x0000 << 8)	
.DEFINE CW_TMR4_UPWM_Out_PWM			(0x0001 << 8)	
.DEFINE CW_TMR4_VPWM_Out_HL				(0x0000 << 9)	
.DEFINE CW_TMR4_VPWM_Out_PWM			(0x0001 << 9)	
.DEFINE CW_TMR4_WPWM_Out_HL				(0x0000 << 10)
.DEFINE CW_TMR4_WPWM_Out_PWM			(0x0001 << 10)
.DEFINE CW_TMR4_POLP_Active_Low			(0x0000 << 14)
.DEFINE CW_TMR4_POLP_Active_High		(0x0001 << 14)
.DEFINE CW_TMR4_DUTYMODE_UCom			(0x0000 << 15)
.DEFINE CW_TMR4_DUTYMODE_Independent	(0x0001 << 15)

// Bit set //
.DEFINE CB_TMR4_UOC0					0	
.DEFINE CB_TMR4_UOC1					1
.DEFINE CB_TMR4_VOC0					2	
.DEFINE CB_TMR4_VOC1					3
.DEFINE CB_TMR4_WOC0					4	
.DEFINE CB_TMR4_WOC1					5
.DEFINE CB_TMR4_SYNC0					6	
.DEFINE CB_TMR4_SYNC1					7		
.DEFINE CB_TMR4_UPWM					8		
.DEFINE CB_TMR4_VPWM					9	
.DEFINE CB_TMR4_WPWM					10
.DEFINE CB_TMR4_POLP_Active				14
.DEFINE CB_TMR4_DUTYMODE				15

// P_POS0_DectCtrl register //							//Timer 0 Position Detection Control Register
// word set //
.DEFINE CW_TMR0_PDCR_PDEN				(0x0001 << 7)
.DEFINE CW_TMR0_PDCR_SPLMOD_Mode1		(0x0000 << 12)
.DEFINE CW_TMR0_PDCR_SPLMOD_Mode2		(0x0001 << 12)
.DEFINE CW_TMR0_PDCR_SPLMOD_Mode3		(0x0002 << 12)
.DEFINE CW_TMR0_PDCR_SPLCK_FCKdiv4		(0x0000 << 14)
.DEFINE CW_TMR0_PDCR_SPLCK_FCKdiv8		(0x0001 << 14)
.DEFINE CW_TMR0_PDCR_SPLCK_FCKdiv16		(0x0002 << 14)
.DEFINE CW_TMR0_PDCR_SPLCK_FCKdiv32		(0x0003 << 14)

// Bit set //
.DEFINE CB_TMR0_PDCR_PDEN				7
.DEFINE CB_TMR0_PDCR_SPLMOD0			12
.DEFINE CB_TMR0_PDCR_SPLMOD1			13
.DEFINE CB_TMR0_PDCR_SPLCK0				14
.DEFINE CB_TMR0_PDCR_SPLCK1				15

// P_POS1_DectCtrl register //							//Timer 1 Position Detection Control Register
// word set //
.DEFINE CW_TMR1_PDCR_PDEN				(0x0001 << 7)
.DEFINE CW_TMR1_PDCR_SPLMOD_Mode1		(0x0000 << 12)
.DEFINE CW_TMR1_PDCR_SPLMOD_Mode2		(0x0001 << 12)
.DEFINE CW_TMR1_PDCR_SPLMOD_Mode3		(0x0002 << 12)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv4		(0x0000 << 14)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv8		(0x0001 << 14)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv16		(0x0002 << 14)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv32		(0x0003 << 14)

// Bit set //
.DEFINE CB_TMR1_PDCR_PDEN				7
.DEFINE CB_TMR1_PDCR_SPLMOD0			12
.DEFINE CB_TMR1_PDCR_SPLMOD1			13
.DEFINE CB_TMR1_PDCR_SPLCK0				14
.DEFINE CB_TMR1_PDCR_SPLCK1				15

// P_POS0_DectData register //							//Timer 0 Position Detection Register
// word set //
.DEFINE CW_TMR0_PDR_TIO0A				0x0001
.DEFINE CW_TMR0_PDR_TIO0B				(0x0001 << 1)
.DEFINE CW_TMR0_PDR_TIO0C				(0x0001 << 2)

// Bit set //
.DEFINE CB_TMR0_PDR_TIO0A				0
.DEFINE CB_TMR0_PDR_TIO0B				1
.DEFINE CB_TMR0_PDR_TIO0C				2

// P_POS1_DectData register //							//Timer 1 Position Detection Register
// word set //
.DEFINE CW_TMR1_PDR_TIO1A				0x0001
.DEFINE CW_TMR1_PDR_TIO1B				(0x0001 << 1)
.DEFINE CW_TMR1_PDR_TIO1C				(0x0001 << 2)

// Bit set //
.DEFINE CB_TMR1_PDR_TIO1A				0
.DEFINE CB_TMR1_PDR_TIO1B				1
.DEFINE CB_TMR1_PDR_TIO1C				2

// P_TMR3_DeadTime register //							//Timer 3 Dead Time Control Register
// word set //
.DEFINE CW_TMR3_DTCR_DTUE				(0x0001 << 12)
.DEFINE CW_TMR3_DTCR_DTVE				(0x0001 << 13)
.DEFINE CW_TMR3_DTCR_DTWE				(0x0001 << 14)

// Bit set //
.DEFINE CB_TMR3_DTCR_DTUE				12
.DEFINE CB_TMR3_DTCR_DTVE				13
.DEFINE CB_TMR3_DTCR_DTWE				14

// P_TMR4_DeadTime register //							//Timer 4 Dead Time Control Register
// word set //
.DEFINE CW_TMR4_DTCR_DTUE				(0x0001 << 12)
.DEFINE CW_TMR4_DTCR_DTVE				(0x0001 << 13)
.DEFINE CW_TMR4_DTCR_DTWE				(0x0001 << 14)

// Bit set //
.DEFINE CB_TMR4_DTCR_DTUE				12
.DEFINE CB_TMR4_DTCR_DTVE				13
.DEFINE CB_TMR4_DTCR_DTWE				14

// P_TPWM_Write register //								//Timer /PWM Module Write Enable Control Register
// word set //
.DEFINE CW_TWCR_TMR3WE					0x0001
.DEFINE CW_TWCR_TMR4WE					(0x0001 << 1)

// Bit set //
.DEFINE CB_TWCR_TMR3WE					0
.DEFINE CB_TWCR_TMR4WE					1