--lpm_add_sub CARRY_CHAIN=MANUAL CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY=ACEX1K LPM_PIPELINE=1 LPM_REPRESENTATION=SIGNED LPM_WIDTH=13 ONE_INPUT_IS_CONSTANT=NO aclr cin clken clock dataa datab result
--VERSION_BEGIN 4.0 cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2004:02:27:16:26:40:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);

--synthesis_resources = lut 14 
SUBDESIGN add_sub_h7i
( 
	aclr	:	input;
	cin	:	input;
	clken	:	input;
	clock	:	input;
	dataa[12..0]	:	input;
	datab[12..0]	:	input;
	result[12..0]	:	output;
) 
VARIABLE 
	add_sub_cella[12..0] : carry_sum;
	external_cin_cell : carry_sum;
	output_dffea[12..0] : dffe;
	main_cin_wire	: WIRE;

BEGIN 
	add_sub_cella[0].cin = ((datab[0..0] & main_cin_wire) # (dataa[0..0] & (datab[0..0] $ main_cin_wire)));
	add_sub_cella[1].cin = ((datab[1..1] & add_sub_cella[0].cout) # (dataa[1..1] & (datab[1..1] $ add_sub_cella[0].cout)));
	add_sub_cella[2].cin = ((datab[2..2] & add_sub_cella[1].cout) # (dataa[2..2] & (datab[2..2] $ add_sub_cella[1].cout)));
	add_sub_cella[3].cin = ((datab[3..3] & add_sub_cella[2].cout) # (dataa[3..3] & (datab[3..3] $ add_sub_cella[2].cout)));
	add_sub_cella[4].cin = ((datab[4..4] & add_sub_cella[3].cout) # (dataa[4..4] & (datab[4..4] $ add_sub_cella[3].cout)));
	add_sub_cella[5].cin = ((datab[5..5] & add_sub_cella[4].cout) # (dataa[5..5] & (datab[5..5] $ add_sub_cella[4].cout)));
	add_sub_cella[6].cin = ((datab[6..6] & add_sub_cella[5].cout) # (dataa[6..6] & (datab[6..6] $ add_sub_cella[5].cout)));
	add_sub_cella[7].cin = ((datab[7..7] & add_sub_cella[6].cout) # (dataa[7..7] & (datab[7..7] $ add_sub_cella[6].cout)));
	add_sub_cella[8].cin = ((datab[8..8] & add_sub_cella[7].cout) # (dataa[8..8] & (datab[8..8] $ add_sub_cella[7].cout)));
	add_sub_cella[9].cin = ((datab[9..9] & add_sub_cella[8].cout) # (dataa[9..9] & (datab[9..9] $ add_sub_cella[8].cout)));
	add_sub_cella[10].cin = ((datab[10..10] & add_sub_cella[9].cout) # (dataa[10..10] & (datab[10..10] $ add_sub_cella[9].cout)));
	add_sub_cella[11].cin = ((datab[11..11] & add_sub_cella[10].cout) # (dataa[11..11] & (datab[11..11] $ add_sub_cella[10].cout)));
	add_sub_cella[12].cin = ((datab[12..12] & add_sub_cella[11].cout) # (dataa[12..12] & (datab[12..12] $ add_sub_cella[11].cout)));
	add_sub_cella[].sin = output_dffea[].Q;
	external_cin_cell.cin = cin;
	external_cin_cell.sin = B"0";
	output_dffea[].CLK = clock;
	output_dffea[].CLRN = (! aclr);
	output_dffea[0].D = (dataa[0..0] $ (datab[0..0] $ main_cin_wire));
	output_dffea[1].D = (dataa[1..1] $ (datab[1..1] $ add_sub_cella[0].cout));
	output_dffea[2].D = (dataa[2..2] $ (datab[2..2] $ add_sub_cella[1].cout));
	output_dffea[3].D = (dataa[3..3] $ (datab[3..3] $ add_sub_cella[2].cout));
	output_dffea[4].D = (dataa[4..4] $ (datab[4..4] $ add_sub_cella[3].cout));
	output_dffea[5].D = (dataa[5..5] $ (datab[5..5] $ add_sub_cella[4].cout));
	output_dffea[6].D = (dataa[6..6] $ (datab[6..6] $ add_sub_cella[5].cout));
	output_dffea[7].D = (dataa[7..7] $ (datab[7..7] $ add_sub_cella[6].cout));
	output_dffea[8].D = (dataa[8..8] $ (datab[8..8] $ add_sub_cella[7].cout));
	output_dffea[9].D = (dataa[9..9] $ (datab[9..9] $ add_sub_cella[8].cout));
	output_dffea[10].D = (dataa[10..10] $ (datab[10..10] $ add_sub_cella[9].cout));
	output_dffea[11].D = (dataa[11..11] $ (datab[11..11] $ add_sub_cella[10].cout));
	output_dffea[12].D = (dataa[12..12] $ (datab[12..12] $ add_sub_cella[11].cout));
	output_dffea[].ENA = clken;
	main_cin_wire = external_cin_cell.cout;
	result[] = add_sub_cella[].sout;
END;
--VALID FILE