------------------------------------------------------------------------------  This file is a part of the LEON VHDL model--  Copyright (C) 1999  European Space Agency (ESA)----  This library is free software; you can redistribute it and/or--  modify it under the terms of the GNU Lesser General Public--  License as published by the Free Software Foundation; either--  version 2 of the License, or (at your option) any later version.----  See the file COPYING.LGPL for the full details of the license.------------------------------------------------------------------------------- Entity: 	mctrl-- File:	mctrl.vhd-- Author:	Jiri Gaisler - ESA/ESTEC-- Description:	External memory controller.------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library grlib;use grlib.amba.all;use grlib.devices.all;use grlib.stdlib.all;library gaisler;use gaisler.memctrl.all;library esa;use esa.memoryctrl.all;entity smc_mctrl is  generic (    hindex    : integer := 0;    pindex    : integer := 0;    romaddr   : integer := 16#000#;    rommask   : integer := 16#E00#;    ioaddr    : integer := 16#200#;    iomask    : integer := 16#E00#;    ramaddr   : integer := 16#400#;    rammask   : integer := 16#C00#;    paddr     : integer := 0;    pmask     : integer := 16#fff#;    wprot     : integer := 0;    invclk    : integer := 0;    fast      : integer := 0;    romasel   : integer := 28;    sdrasel   : integer := 29;    srbanks   : integer := 4;    ram8      : integer := 0;    ram16     : integer := 0;    sden      : integer := 0;    sepbus    : integer := 0;    sdbits    : integer := 32;    sdlsb     : integer := 2;          -- set to 12 for the GE-HPE board    oepol     : integer := 0;    syncrst   : integer := 0  );  port (    rst       : in  std_ulogic;    clk       : in  std_ulogic;    memi      : in  memory_in_type;    memo      : out memory_out_type;    ahbsi     : in  ahb_slv_in_type;    ahbso     : out ahb_slv_out_type;    apbi      : in  apb_slv_in_type;    apbo      : out apb_slv_out_type;    wpo       : in  wprot_out_type;    sdo       : out sdram_out_type;    eth_aen   : out std_logic; -- for smsc eth    eth_readn : out std_logic; -- for smsc eth    eth_writen: out std_logic;  -- for smsc eth    eth_nbe   : out std_logic_vector(3 downto 0) -- for smsc eth  );end;architecture rtl of smc_mctrl isconstant REVISION  : integer := 0;constant prom : integer := 1;constant memory : integer := 0;constant hconfig : ahb_config_type := (  0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),  4 => ahb_membar(romaddr, '1', '1', rommask),  5 => ahb_membar(ioaddr,  '0', '0', iomask),  6 => ahb_membar(ramaddr, '1', '1', rammask),  others => zero32);constant pconfig : apb_config_type := (  0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),  1 => apb_iobar(paddr, pmask));constant RAMSEL5 : boolean := srbanks = 5;constant SDRAMEN : boolean := (sden /= 0);constant BUS16EN : boolean := (ram16 /= 0);constant BUS8EN  : boolean := (ram8 /= 0);constant WPROTEN : boolean := (wprot /= 0);constant WENDFB  : boolean := false;constant SDSEPBUS: boolean := (sepbus /= 0);constant BUS64   : boolean := (sdbits = 64);constant rom : integer := 0;constant io  : integer := 1;constant ram : integer := 2;type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);-- memory configuration register 1 typetype mcfg1type is record  romrws           : std_logic_vector(3 downto 0);  romwws           : std_logic_vector(3 downto 0);  romwidth         : std_logic_vector(1 downto 0);  romwrite         : std_logic;  ioen             : std_logic;  iows             : std_logic_vector(3 downto 0);  bexcen           : std_logic;  brdyen           : std_logic;  iowidth          : std_logic_vector(1 downto 0);end record;-- memory configuration register 2 typetype mcfg2type is record  ramrws           : std_logic_vector(1 downto 0);  ramwws           : std_logic_vector(1 downto 0);  ramwidth         : std_logic_vector(1 downto 0);  rambanksz        : std_logic_vector(3 downto 0);  rmw              : std_logic;  brdyen           : std_logic;  srdis            : std_logic;  sdren            : std_logic;end record;-- memory status register type-- local registerstype reg_type is record  address          : std_logic_vector(31 downto 0);  -- memory address  data             : std_logic_vector(31 downto 0);  -- latched memory data  writedata        : std_logic_vector(31 downto 0);  writedata8       : std_logic_vector(15 downto 0);  -- lsb write data buffer  sdwritedata      : std_logic_vector(63 downto 0);  readdata         : std_logic_vector(31 downto 0);  brdyn            : std_logic;  ready            : std_logic;  ready8           : std_logic;  bdrive           : std_logic_vector(3 downto 0);  nbdrive          : std_logic_vector(3 downto 0);  ws               : std_logic_vector(3 downto 0);  romsn		   : std_logic_vector(1 downto 0);  ramsn		   : std_logic_vector(4 downto 0);  ramoen	   : std_logic_vector(4 downto 0);  size		   : std_logic_vector(1 downto 0);  busw		   : std_logic_vector(1 downto 0);  oen              : std_logic;  iosn		   : std_logic_vector(1 downto 0);  read             : std_logic;  wrn              : std_logic_vector(3 downto 0);  writen           : std_logic;  bstate           : memcycletype;  area  	   : std_logic_vector(0 to 2);  mcfg1		   : mcfg1type;  mcfg2		   : mcfg2type;  bexcn            : std_logic;		-- latched external bexcn  echeck           : std_logic;  brmw             : std_logic;  haddr            : std_logic_vector(31 downto 0);  hsel             : std_logic;  srhsel           : std_logic;  hwrite           : std_logic;  hburst           : std_logic_vector(2 downto 0);  htrans           : std_logic_vector(1 downto 0);  hresp 	   : std_logic_vector(1 downto 0);  sa    	   : std_logic_vector(14 downto 0);  sd    	   : std_logic_vector(63 downto 0);  mben	   	   : std_logic_vector(3 downto 0);  eth_aen    : std_logic; -- for smsc eth  eth_readn  : std_logic; -- for smsc eth  eth_writen : std_logic; -- for smsc eth  eth_nbe    : std_logic_vector(3 downto 0);-- for smsc ethend record;signal r, ri : reg_type;signal wrnout : std_logic_vector(3 downto 0);signal sdmo : sdram_mctrl_out_type;signal sdi  : sdram_in_type;signal sdapbo   :  apb_slv_out_type;-- vectored output enable to data pads signal rbdrive, ribdrive : std_logic_vector(31 downto 0);signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);attribute syn_preserve : boolean;attribute syn_preserve of rbdrive : signal is true;attribute syn_preserve of rsbdrive : signal is true; -- **** tame: added signal to invert polarity-- signal bprom_cs : std_ulogic;begin  ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, sdapbo, rbdrive, rsbdrive)  variable v : reg_type;		-- local variables for registers  variable start : std_logic;  variable dataout : std_logic_vector(31 downto 0); -- data from memory  variable regsd : std_logic_vector(31 downto 0);   -- data from registers  variable memdata : std_logic_vector(31 downto 0);   -- data to memory  variable rws : std_logic_vector(3 downto 0);		-- read waitstates  variable wws : std_logic_vector(3 downto 0);		-- write waitstates  variable wsnew : std_logic_vector(3 downto 0);		-- write waitstates  variable adec : std_logic_vector(1 downto 0);  variable rams : std_logic_vector(4 downto 0);  variable bready, leadin : std_logic;  variable csen : std_logic;			-- Generate chip selects  variable aprot   : std_logic_vector(14 downto 0); --  variable wrn   : std_logic_vector(3 downto 0); --  variable bexc, addrerr : std_logic;  variable ready : std_logic;  variable writedata : std_logic_vector(31 downto 0);  variable bwdata : std_logic_vector(31 downto 0);  variable merrtype  : std_logic_vector(2 downto 0); -- memory error type  variable noerror : std_logic;  variable area  : std_logic_vector(0 to 2);  variable bdrive : std_logic_vector(3 downto 0);  variable ramsn : std_logic_vector(4 downto 0);  variable romsn, busw : std_logic_vector(1 downto 0);  variable iosn : std_logic;  variable lock : std_logic;  variable wprothitx : std_logic;  variable brmw : std_logic;  variable bidle: std_logic;  variable haddr   : std_logic_vector(31 downto 0);  variable hsize   : std_logic_vector(1 downto 0);  variable hwrite  : std_logic;  variable hburst  : std_logic_vector(2 downto 0);  variable htrans  : std_logic_vector(1 downto 0);  variable sdhsel, srhsel, hready  : std_logic;  variable vbdrive : std_logic_vector(31 downto 0);  variable vsbdrive : std_logic_vector(63 downto 0);  variable bdrive_sel : std_logic_vector(3 downto 0);  begin -- Variable default settings to avoid latches    v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);    ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';    v.ready := '0'; v.echeck := '0';    merrtype := "---"; bready := '1';    vbdrive := rbdrive; vsbdrive := rsbdrive;         v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;    if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or       (((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and	 (r.ramsn(4) = '0') and RAMSEL5)    then      bready := '0';    else bready := '1'; end if;    v.hresp := HRESP_OKAY;    if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then      haddr := r.haddr;  hsize := r.size; hburst := r.hburst;      htrans := r.htrans; hwrite := r.hwrite;      area := r.area;    else      haddr := ahbsi.haddr;  hsize := ahbsi.hsize(1 downto 0);      hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;      area := ahbsi.hmbsel(0 to 2);    end if;    if SDRAMEN then      if fast = 1 then        sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and	   ahbsi.htrans(1) and ahbsi.hmbsel(2);      else        sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and	  r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);      end if;      srhsel := ahbsi.hsel(hindex) and not sdhsel;    else  sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;-- decode memory area parameters    leadin := '0'; rws := "----"; wws := "----"; adec := "--";    busw := (others => '-'); brmw := '0';    if area(rom) = '1' then      busw := r.mcfg1.romwidth;    end if;    if area(ram) = '1' then      adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &              genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));      if sdhsel = '1' then busw := "10";      else        busw := r.mcfg2.ramwidth;        if ((r.mcfg2.rmw and hwrite) = '1') and	 ((BUS16EN and (busw = "01") and (hsize = "00")) or	  ((busw(1) = '1') and (hsize(1) = '0'))        )        then brmw := '1'; end if;	 -- do a read-modify-write cycle      end if;    end if;    if area(io) = '1' then      leadin := '1';      busw := r.mcfg1.iowidth;    end if;-- decode waitstates, illegal access and cacheability    if r.area(rom) = '1' then      rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;      if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;    end if;    if r.area(ram) = '1' then      rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;    end if;