?? nand.c
字號(hào):
Uart_Printf("SMC(K9S1208V0M) NAND Lock Test !!!\n");
Uart_Printf("Select Lock type, Softlock(1)/Lock-tight(2) : ");
num=Uart_GetIntNum();;
Uart_Printf("\nEnter programmable start block address ");
S_block = Uart_GetIntNum();
Uart_Printf("Enter programmable end block address ");
E_block = Uart_GetIntNum();
rNFSBLK=(S_block<<5);
rNFEBLK=(E_block<<5);
if(num==1){
rNFCONT|=(1<<12);
Uart_Printf("Software Locked\n ");
}
if(num==2){
rNFCONT|=(1<<13);
Uart_Printf("Lock-tight: To clear Lock-tight, reset S3C2440!!!\n ");
}
Uart_Printf("%d block ~ %d block are Programmable\n ", S_block, (E_block-1));
}
void Test_NF8_SoftUnLock(void)
{
U32 S_block, E_block;
Uart_Printf("SMC(K9S1208V0M) NAND SoftUnLock Test !!!\n");
rNFSBLK=0x0;
rNFEBLK=0x0;
rNFCONT&=~(1<<12);
if(rNFCONT&(1<<13)){
rNFCONT&=~(1<<13);
Uart_Printf("Lock-tight\n ");
Uart_Printf("You can't unlock Protected blocks !!!\n ");
Uart_Printf("%d block ~ %d block are Programmable\n ", (rNFSBLK>>5), ((rNFEBLK>>5)-1));
}
else Uart_Printf("All blocks are Programmable\n ");
}
void PrintSubMessage(void)
{
int i;
i=0;
Uart_Printf("\n\n");
while(1)
{ //display menu
Uart_Printf("%2d:%s",i,n8_func[i][1]);
i++;
if((int)(n8_func[i][0])==0)
{
Uart_Printf("\n");
break;
}
if((i%4)==0) Uart_Printf("\n");
}
}
static int NF8_EraseBlock(U32 block)
{
U32 blockPage=(block<<5);
int i;
NFConDone=0;
rNFCONT|=(1<<9);
rNFCONT|=(1<<10);
pISR_NFCON= (unsigned)NFCon_Int;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
#if BAD_CHECK
if(NF8_IsBadBlock(block))
return FAIL;
#endif
NF_nFCE_L();
NF_CMD(0x60); // Erase one block 1st command, Block Addr:A9-A25
// Address 3-cycle
NF_ADDR(blockPage&0xff); // Page number=0
NF_ADDR((blockPage>>8)&0xff);
NF_ADDR((blockPage>>16)&0xff);
NF_CLEAR_RB();
NF_CMD(0xd0); // Erase one blcok 2nd command
// NF_DETECT_RB();
while(NFConDone==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
if(rNFSTAT&0x8) return FAIL;
NF_CMD(0x70); // Read status command
if (NF_RDDATA()&0x1) // Erase error
{
NF_nFCE_H();
Uart_Printf("[ERASE_ERROR:block#=%d]\n",block);
// NF8_MarkBadBlock(block);
return FAIL;
}
else
{
NF_nFCE_H();
return OK;
}
}
void __irq NFCon_Int(void)
{
NFConDone=1;
rINTMSK|=BIT_NFCON;
ClearPending(BIT_NFCON);
if(rNFSTAT&0x8) Uart_Printf("Illegal Access is detected!!!\n");
// else Uart_Printf("RnB is Detected!!!\n");
}
static int NF8_IsBadBlock(U32 block)
{
int i;
unsigned int blockPage;
U8 data;
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x50); // Spare array read command
NF_ADDR((512+5)&0xf); // Read the mark of bad block in spare array(M addr=5), A4-A7:Don't care
NF_ADDR(blockPage&0xff); // The mark of bad block is in 0 page
NF_ADDR((blockPage>>8)&0xff); // For block number A[24:17]
NF_ADDR((blockPage>>16)&0xff); // For block number A[25]
NF_DETECT_RB(); // Wait tR(max 12us)
data=NF_RDDATA();
NF_nFCE_H();
if(data!=0xff)
{
Uart_Printf("[block %d has been marked as a bad block(%x)]\n",block,data);
return FAIL;
}
else
{
return OK;
}
}
static int NF8_MarkBadBlock(U32 block)
{
int i;
U32 blockPage=(block<<5);
se8Buf[0]=0xff;
se8Buf[1]=0xff;
se8Buf[2]=0xff;
se8Buf[5]=0x44; // Bad blcok mark=44
NF_nFCE_L();
NF_CMD(0x50); //????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0x0); // The mark of bad block is
NF_ADDR(blockPage&0xff); // marked 5th spare array
NF_ADDR((blockPage>>8)&0xff); // in the 1st page.
NF_ADDR((blockPage>>16)&0xff); //
for(i=0;i<16;i++)
{
NF_WRDATA(se8Buf[i]); // Write spare array
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
NF_CMD(0x70);
for(i=0;i<3;i++); //twhr=60ns////??????
if (NF_RDDATA()&0x1) // Spare arrray write error
{
NF_nFCE_H();
Uart_Printf("[Program error is occurred but ignored]\n");
}
else
{
NF_nFCE_H();
}
Uart_Printf("[block #%d is marked as a bad block]\n",block);
return OK;
}
static int NF8_ReadPage(U32 block,U32 page,U8 *buffer)
{
int i;
unsigned int blockPage;
U32 Mecc, Secc;
U8 *bufPt=buffer;
U8 se[16], ecc0, ecc1, ecc2, ecc3,a,b,c,d,e;
blockPage=(block<<5)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_ADDR((blockPage>>16)&0xff); //
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(512/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#elif TRANS_MODE==ASM
__RdPage512(bufPt);
#endif
/*
NF_MECC_Lock();
rNFMECCD0=NF_RDDATA();
NF_nFCE_H();
if ((rNFESTAT0&0x3) == 0x0) return OK;
else return FAIL;
*/
NF_MECC_Lock();
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
NF_RDDATA(); // read 4~7
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
NF_nFCE_H();
if ((rNFESTAT0&0xf) == 0x0){
Uart_Printf("ECC OK!\n");
return OK;
}
else {
Uart_Printf("ECC FAIL!\n");
return FAIL;
}
}
static int NF8_WritePage(U32 block,U32 page,U8 *buffer)
{
int i;
U32 blockPage, Mecc, Secc;
U8 *bufPt=buffer;
NFConDone=0;
rNFCONT|=(1<<9);
rNFCONT|=(1<<10);
pISR_NFCON= (unsigned)NFCon_Int;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
blockPage=(block<<5)+page;
NF_nFCE_L();
NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & page num.
NF_ADDR((blockPage>>16)&0xff); //
#if TRANS_MODE==C_LANG
for(i=0;i<512;i++) {
NF_WRDATA8(*bufPt++); // Write one page to NFM from buffer
}
#elif TRANS_MODE==DMA
// Memory to Nand dma setting
rSRCPND=BIT_DMA0; // Init DMA src pending.
rDISRC0=(unsigned)bufPt; // Nand flash data register
rDISRCC0=(0<<1) | (0<<0); //arc=AHB,src_addr=inc
rDIDST0=NFDATA;
rDIDSTC0=(0<<1) | (1<<0); //dst=AHB,dst_addr=fix;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(0<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(512/4);
// only unit transfer in writing!!!!
//Handshake,AHB,interrupt,(unit),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
rSRCPND=BIT_DMA0;
#endif
/*
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5
// ecc [0] [1] [2] [3] x [Bad marking]
Mecc = rNFMECC0;
se8Buf[0]=(U8)(Mecc&0xff);
se8Buf[1]=(U8)((Mecc>>8) & 0xff);
se8Buf[2]=(U8)((Mecc>>16) & 0xff);
se8Buf[3]=(U8)((Mecc>>24) & 0xff);
se8Buf[5]=0xffff; // Marking good block
//Write extra data(ECC, bad marking)
for(i=0;i<16;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(ECC and Mark)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA()&0x1) {// Page write error
Uart_Printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF8_MarkBadBlock(block);
NF_nFCE_H();
return FAIL;
} else {
NF_nFCE_H();
return OK;
}
*/
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [0] [1] [2] [3] x [Bad marking] SECC0 SECC1
Mecc = rNFMECC0;
se8Buf[0]=(U8)(Mecc&0xff);
se8Buf[1]=(U8)((Mecc>>8) & 0xff);
se8Buf[2]=(U8)((Mecc>>16) & 0xff);
se8Buf[3]=(U8)((Mecc>>24) & 0xff);
se8Buf[5]=0xff; // Marking good block
NF_SECC_UnLock();
//Write extra data(ECC, bad marking)
for(i=0;i<4;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(Main ECC)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_SECC_Lock();
Secc=rNFSECC;
se8Buf[8]=(U8)(Secc&0xff);
se8Buf[9]=(U8)((Secc>>8) & 0xff);
for(i=4;i<16;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(Spare ECC and Mark)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
// NF_DETECT_RB();
while(NFConDone==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
if(rNFSTAT&0x8) return FAIL;
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA()&0x1) {// Page write error
NF_nFCE_H();
Uart_Printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF8_MarkBadBlock(block);
return FAIL;
} else {
NF_nFCE_H();
return OK;
}
}
static U16 NF8_CheckId(void)
{
int i;
U16 id, id4th;
NF_nFCE_L();
NF_CMD(0x90);
NF_ADDR(0x0);
for (i=0; i<10; i++);
Uart_Printf("NFSTAT: 0x%x\n", rNFSTAT);
id=NF_RDDATA8()<<8; // Maker code 0xec
id|=NF_RDDATA8(); // Devide code(K9S1208V:0x76), (K9K2G16U0M:0xca)
NF_nFCE_H();
return id;
}
void Nand_Reset(void)
{
int i;
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0xFF); //reset command
for(i=0;i<10;i++); //tWB = 100ns. //??????
NF_DETECT_RB();
NF_nFCE_H();
}
static void NF8_Init(void)
{
// for S3C2440
rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
// TACLS [14:12] CLE&ALE duration = HCLK*TACLS.
// TWRPH0 [10:8] TWRPH0 duration = HCLK*(TWRPH0+1)
// TWRPH1 [6:4] TWRPH1 duration = HCLK*(TWRPH1+1)
// AdvFlash(R) [3] Advanced NAND, 0:256/512, 1:1024/2048
// PageSize(R) [2] NAND memory page size
// when [3]==0, 0:256, 1:512 bytes/page.
// when [3]==1, 0:1024, 1:2048 bytes/page.
// AddrCycle(R) [1] NAND flash addr size
// when [3]==0, 0:3-addr, 1:4-addr.
// when [3]==1, 0:4-addr, 1:5-addr.
// BusWidth(R/W) [0] NAND bus width. 0:8-bit, 1:16-bit.
rNFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
// Lock-tight [13] 0:Disable lock, 1:Enable lock.
// Soft Lock [12] 0:Disable lock, 1:Enable lock.
// EnablillegalAcINT[10] Illegal access interupt control. 0:Disable, 1:Enable
// EnbRnBINT [9] RnB interrupt. 0:Disable, 1:Enable
// RnB_TrandMode[8] RnB transition detection config. 0:Low to High, 1:High to Low
// SpareECCLock [6] 0:Unlock, 1:Lock
// MainECCLock [5] 0:Unlock, 1:Lock
// InitECC(W) [4] 1:Init ECC decoder/encoder.
// Reg_nCE [1] 0:nFCE=0, 1:nFCE=1.
// NANDC Enable [0] operating mode. 0:Disable, 1:Enable.
// rNFSTAT = 0;
// Nand_Reset();
}
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