?? msp430x20x3_clks.s43
字號:
;*******************************************************************************
; MSP430F20xx Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
;
; Description: Buffer ACLK on P1.0, default SMCLK(DCO) on P1.4 and MCLK/10 on
; P1.1.
; ACLK = LFXT1 = 32768, MCLK = SMCLK = default DCO
; //* External watch crystal installed on XIN XOUT is required for ACLK *//
;
; MSP430F20xx
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P1.4/SMCLK|-->SMCLK = Default DCO
; | P1.1|-->MCLK/10 = DCO/10
; | P1.0/ACLK|-->ACLK = 32kHz
;
; M. Buccini / L. Westlund
; Texas Instruments Inc.
; October 2005
; Built with IAR Embedded Workbench Version: 3.40A
;*******************************************************************************
#include "msp430x20x3.h"
;-------------------------------------------------------------------------------
ORG 0F800h ; Program Reset
;-------------------------------------------------------------------------------
RESET mov.w #0280h,SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupPx bis.b #013h,&P1DIR ; P1.0,1,4 output direction
bis.b #011h,&P1SEL ; P1.0,4 = ACLK,SMCLK
;
Mainloop bis.b #002h,&P1OUT ; P1.1 = 1
bic.b #002h,&P1OUT ; P1.1 = 0
jmp Mainloop ; Repeat
;
;
;-------------------------------------------------------------------------------
; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
END
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