/*******************************************************************************
Copyright(c) 2000 - 2002 Analog Devices. All Rights Reserved.
Developed by Joint Development Software Application Team, IPDC, Bangalore, India
for Blackfin DSPs  ( Micro Signal Architecture 1.0 specification).
    By using this module you agree to the terms of the Analog Devices License
Agreement for DSP Software. 
********************************************************************************
Module Name     : ld_div32.asm
Label name      : __ld_div32
Version         : 1.1
Change History  :

                Version     Date          Author        Comments
                1.1         01/22/2002    Srinivas      Modified to match
                                                        silicon cycle count
                1.0         06/26/2001    Srinivas      Original 

Description     : This function performs signed division  of 32 bit fractional 
                  integer number using  DIVS and DIVQ. Denominator must be
                  positive between 0x40000000 & 0x7FFFFFFF.
                  i.e normalised.

                    L_denom -> 32 bit Denominator
                    L_num   -> 32 bit Numerator
                    denom_hi-> high 16 bits of denominator

Algorithm       :
                    - find = 1/L_denom.

                    First approximation :     approx = 1 / denom_hi 
                            1/L_denom = approx * (2.0 - L_denom * approx )
                    -  result = L_num * (1/L_denom)

Prototype       : fract32 _ld_div32(fract 32 numerator, fract32 denominator)

Registers Used  : A0, A1, R0-R4, P0, LC0.

Performance     :
                    Code size   : 94 bytes
                    Cycle count : 44 Cycles.
*******************************************************************************/
.section L1_code;
.global __ld_div32;
.align 8;

__ld_div32:

    [--SP] = R4;
    P0 = 15;
    R2.H = 0X3FFF;          //0.5
    R2.L = 0XFFFF;
    R3 = R1;                //DEN
    R3 =R3 >>> 16;          //DEN.H in R3.L
/* Loop to get appr = (0.5/DEN.H)  */
    DIVS(R2,R3);            //Get sign bit

    LSETUP(DIV_ST_END, DIV_ST_END) LC0 = P0;
DIV_ST_END:
        DIVQ(R2,R3);
    R4.L = 0XFFFF;          //R4 = 1 in 1.31 format 
    A1 = R1.L * R2.L (FU);
                            //DEN.L * appr
    A1 = A1 >> 15;
    R3 = (A1 += R1.H * R2.L);
                            //DEN * appr = DEN.H * appr + DEN.L * appr
    R4.H = 0X7FFF;          //R4 = 1
    R3 = R4 - R3;           //RES = 1 - (DEN * appr)
    A0 = R3.L * R2.L (fu);
                            //RES.L * appr
    A0 = A0 >> 15;
    R2 = (A0 += R3.H * R2.L);
                            //1/DEN = RES.L * appr + RES.H * appr 
    R4 = [SP++];
                            //restore R4 value from stack
    A1 = R0.H * R2.L (m);
                            //X.H * Y.L
    A1 += R2.H * R0.L (m);
                            //X.H * Y.L + Y.H * X.L
    A1 = A1 >>> 15;
                            //Result in A1.L
    A1 += R0.H * R2.H;  
                            //X.H * Y.H + X.H * Y.L + Y.H * X.L
    A1 = A1 << 2;           //X/Y
    A0 = A1;
    R0 = A0;                //Result in R0
    RTS;
    NOP;                    //to avoid one stall if LINK or UNLINK happens to be
                            //the next instruction after RTS in the memory.
__ld_div32.end: